Infineon Technologies C166S V2 User Manual page 108

two independent read/write ports; this allows parallel read and write operation without
delays. Write accesses to the internal SRAM can be buffered in a Write BACK Buffer until
read accesses are finished.
• Bandwidth conflicts in the DPRAM Area
All instructions except the CoXXX instructions can read only one memory operand per
cycle. A conflict between the read and one write access cannot occur because the
DPRAM has two independent read/write ports.
I ........
n-1
I ADD op1,R1
n
I ADD R6,R0
n+1
I ADD R6,op2
n+2
I MOV R3,[R0]
n+3
I ........
n+4
T
n
DECODE I =
n
ADD op1,R1
ADDRESS
I
n-1
MEMORY I
n-2
EXECUTE
I
n-3
WRITE BACK I
n-4
Note: Only other pipeline stall conditions can generate a DPRAM bandwidth conflict.
The DPRAM is a synchronous pipelined memory. The read access starts with the
valid addresses on the address stage. The data are delivered in the Memory
stage. If a memory read access is stalled in the Memory stage and the following
instruction on the Address stage tries to start a memory read, the new read access
must be delayed as well. But, this conflict is hidden by an already existing stall of
the pipeline.
User Manual
T T
n+1 n+2
I = I =
n+1 n+2
ADD R6,R0 ADD R6,op2
I = I =
n n+1
ADD op1,R1 ADD R6,R0
I I =
n-1 n
ADD op1,R1
I I
n-2 n-1
I I
n-3 n-2
4-108
Instruction Pipeline
T T
n+3 n+4
I = I
n+3 n+4
MOV R3,[R0]
I = I =
n+2 n+3
ADD R6,op2 MOV R3,[R0]
I = I =
n+1 n+2
ADD R6,R0 ADD R6,op2
I = I =
n n+1
ADD op1,R1 ADD R6,R0
I I =
n-1 n
ADD op1,R1
User Manual
C166S V2
T
n+5
I
n+5
I
n+4
I =
n+3
MOV R3,[R0]
I =
n+2
ADD R6,op2
I =
n+1
ADD R6,R0
V 1.7, 2001-01