Infineon Technologies C166S V2 User Manual page 59

The Offset Register QX0 and QX1
These two non-bit addressable registers are used only for CoXXX operations which
access operands using indirect addressing mode. The QX offset registers are used in
conjunction with the IDX pointers.
QX0
Offset Register
15 14 13 12
QX1
Offset Register
15 14 13 12
Field
QX
0
Note: During the initialization of the QX registers, instruction flow stalls are possible. For
the proper operation, refer to the
Physical addresses are generated from indirect address pointers IDX via the following
algorithm:
1) Determine the used IDXx pointer
2) An intermediate long address is calculated for the parallel data move opera-
tion of CoXXXM instructions before the long 16-bit address is generated
[optional step!]:
- If required, indirect address pointers ('IDXx±') are de/incremented by D=2.
- If required, indirect address pointers ('IDXx± QXx') are de/incremented by
D= QXx.
User Manual
ESFR
11 10 9 8
QX
rw
ESFR
11 10 9 8
QX
rw
Bits Type Description
[15:1] rw Modifiable portion of register QXx
Specifies the 16-bit offset address for indirect
addressing modes.
[0] r Fixed to 0
Section
7 6 5
7 6 5
4.1.4.
2-59
User Manual
C166S V2
Central Processing Unit
Reset Value: 0000
4 3 2 1
Reset Value: 0000
4 3 2 1
V 1.7, 2001-01
H
0
0
r
H
0
0
r