Infineon Technologies C166S V2 User Manual page 25

instructions can be prefetched. The PMU address stays stable (T
double word can be buffered (T
T
PMU Address I
PMU Data 64bit I
PREFETCH I
96 bit Buffer ...
I
FETCH I
Instruction
Buffer
FIFO contents I
...
I
Fetch from FIFO I
DECODE I
ADDRESS I
MEMORY I
EXECUTE I
WRITE BACK
Figure 2-4 Sequential Instruction Execution
User Manual
) in the 96-bit Prefetch buffer again.
n+7
T T
n n+1 n+2
I I
a+16 a+24 a+32
I I
d+1 d+2 d+3
I I
n+6 n+9 n+12
... I
n+13
I
n+9 n+11
I I
n+5 n+6 n+9
I I
n+7 n+10
I I
n+8 n+11
I I
n+3 n+4 n+5
... ...
I I
n+5 n+8 n+11
I I
n+4 n+5 n+6
I I
n+3 n+4 n+5
I I
n+2 n+3 n+4
I I
n+1 n+2 n+3
I I
n n+1 n+2
I I
n n+1
T T T
n+3 n+4 n+5
I I I
a+40 a+40 a+40
I I I
d+4 d+5 d+5
I I I
n+14 n+15 n+15
I ... ...
n+15
I I
n+19 n+19
I I -
n+12 n+14
I
n+13
I I I
n+6 n+7 n+7
... ... ...
I I I
n+13 n+14 n+14
I I I
n+7 n+7 n+8
I I I
n+6 n+6 n+7
I I I
n+5 n+6 n+6
I I I
n+4 n+5 n+6
I I I
n+3 n+4 n+5
I I I
n+2 n+3 n+4
2-25
User Manual
C166S V2
Central Processing Unit
) until a whole 64-bit
n+4
T T
n+6 n+7
I I
a+40 a+48
I I
d+5 d+5
I I
n+16 n+17
... ...
I I
n+19 n+19
I I
n+15 n+16
I I
n+8 n+9
... ...
I I
n+15 n+16
I I
n+9 n+10
I I
n+8 n+9
I I
n+7 n+8
I I
n+6 n+7
I I
n+6 n+6
I I
n+5 n+6
V 1.7, 2001-01
T
n+8
I
a+48
I
d+7
I
n+18
...
I
n+21
I
n+17
I
n+10
...
I
n+17
I
n+11
I
n+10
I
n+9
I
n+8
I
n+7
I
n+6