Infineon Technologies C166S V2 User Manual page 322

CoASHR
Group
Syntax
Source Operand(s)
Destination Operand(s)
Operation
(count) ← (op1)
(C) ← 0
DO WHILE (count) ≠ 0
END WHILE
Description
Arithmetically shifts the ACC register right by the number of times as specified by the
operand op1. To preserve the sign of the ACC register, the most significant bits of the
result are filled with sign 0 if the original most significant bit was a 0 or with sign 1 if the
original most significant bit was 1. Only shift values from 0 to 16 (inclusive) are allowed.
op1 can be either a 5-bit unsigned immediate data (the shift range is from 0 to 16 in this
case) or the four least significant bits (the shift range is from 0 to 15 in that case) of any
register directly or indirectly addressed operand. The MS bit of the MCW register does
not affect the result.
MAC Flags
MV MSL
0 -
MV Always cleared.
MSL Not affected.
ME Set if the MAE is used. Cleared otherwise.
MSV Not affected.
MC Always cleared.
MZ Set if result equals zero. Cleared otherwise.
MN Set if the most significant bit of the result is set. Cleared otherwise.
User Manual
Accumulator Arithmetic Shift Right
Shift Instructions
CoASHR op1
op1 → shift counter
ACC → 40-bit signed value
(ACC[n]) ← (ACC[n+1]) [n=0...38]
(count) ← (count) -1
ME MSV
* -
Detailed Instruction Description
MC MZ
0 *
8-322
User Manual
C166S V2
CoASHR
MN Sat.
* no
V 1.7, 2001-01