Infineon Technologies C166S V2 User Manual page 141

EOPIC
Interrupt Control Register
15 14 13 12
0 0 0
r r r
1)
The EOPIC register is assigned to one of the interrupt nodes. The assignment is product specific.
Field
GPX
1)
EOPIR
EOPIE
ILVL
GLVL
XGLVL
1)
Bit EOPIR supports bit-protection
PECISNC
PEC Interrupt Sub Node Control
15 14 13 12
C7IR C7IE C6IR C6IE C5IR C5IE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE C0IR C0IE
rwh rw rwh
User Manual
1)
11 10 9
0 0 0 0
r r r r
Bits Type Description
[8] rw
[7] rwh
[6] rw
[5:2] rw
[1:0] rw
[8],[1:0]
11 10 9
rw rwh rw rwh
Interrupt and Exception Handling
bESFR
8 7 6
GPX EOP EOP
IR IE
rw rwh rw
Group Priority Extension
Defines the value of high-order group level bit
Interrupt Request Flag
0 No request pending
1 The source has raised an interrupt request
Interrupt Enable Control Bit
0 Interrupt request is disabled
1 Interrupt request is enabled
Interrupt Priority Level
F Highest priority level
H
... ...
0 Lowest priority level
H
Group Priority Level
3 Highest priority level
H
... ...
0 Lowest priority level
H
Extended Group Priority Level
7 Highest priority level
H
... ...
0 Lowest priority level
H
bSFR
8 7 6
rw rwh rw
5-141
User Manual
Reset Value: 0000
5 4 3 2
ILVL
rw
Reset Value: 0000
5 4 3 2
rwh rw rwh rw
C166S V2
H
1 0
GLVL
rw
H
1 0
rwh rw
V 1.7, 2001-01