System Bus Ac Specifications - Intel CELERON 1.10 GHZ Datasheet

® ®
Intel Celeron Processor up to 1.10 GHz
2.12

System Bus AC Specifications

The Celeron processor system bus timings specified in this section are defined at the Intel Celeron
processor edge fingers and the processor core pins. Timings specified at the processor edge fingers
only apply to the S.E.P. Package and timings given at the processor core pins apply to all S.E.P.
Package and PGA packages. Unless otherwise specified, timings are tested at the processor core
during manufacturing. Timings at the processor edge fingers are specified by design
characterization. See
66 MHz system bus operation, the Intel Celeron processor timings at the processor edge
fingers are identical to the Pentium II processor timings at the edge fingers. See the Pentium
II Processor at 233, 266, 300, and 333 MHz (Order Number 243335) for more detail.
Table 9 through
system bus. These specifications are broken into the following categories:
contain the system bus clock specifications,
specifications,
timings for the Reset conditions,
Table 26 cover TAP timing. For each pair of tables, the first table contains timing specifications for
measurement or simulation at the processor edge fingers. The second table contains specifications
for simulation at the processor core pads.
All Intel Celeron processor system bus AC specifications for the AGTL+ signal group are relative
to the rising edge of the BCLK input. All AGTL+ timings are referenced to V
'1' logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available in
Quad format as the Intel Celeron
Form). AGTL+ layout guidelines are also available in AP-585, Pentium
Guidelines (Order Number 243330).
Care should be taken to read all notes associated with a particular timing parameter.
34
Section 7.0 for the Intel Celeron processor signal definitions. Note that at
Table 26 list the AC specifications associated with the Intel Celeron processor
Table 17 and Table 18 are the CMOS signal group specifications,
Table 22
®
Processor I/O Buffer Models, Quad XTK Format (Electronic
Table 13 and Table 14 contain the AGTL+
and Table 23 cover APIC bus timing, and
®
Table 9 through Table 12
Table 20 contains
Table 25 and
for both '0' and
REF
®
II Processor AGTL+
Datasheet