Module-By-Module Data Guarantee - Mitsubishi Electric MELSEC iQ-R-R00CPU User Manual

Module-by-module data guarantee

In data communication, data is handled in units of 64 bits. Therefore, when data larger than 64 bits is handled, old and new
data may be mixed for each CPU module depending on the timing between data reading by the host CPU module and data
writing by other CPU modules/data receiving from other CPU modules. (Data inconsistency) To avoid this problem, the
system conducts the refresh operation by exchanging handshake signals between the CPU modules for guaranteeing refresh
data on a module-by-module basis.
CPU No.1
Scan time: 1ms
The CPU module unit guarantee is
enabled:
CPU buffer memory
(9) All the CPU modules have
received the data, and the CPU
No.1 updates (refreshes) the data
in the END processing.
⇒ 1 → 101
(2) The CPU No.1 reflects
(refreshes) the data in the
END processing of the
CPU No.1.
The CPU module unit guarantee
is enabled: Device
(3) The CPU No.1 does not
update (refresh) the data in the
D0,D1
END processing until the other
CPU modules receive the data.
Program
SM 400
Data change when the CPU module unit guarantee
is enabled
Device memory
(Scan)
First scan
Second scan
Third scan
:
10th scan
11th scan
:
50th scan
51st scan
:
100th scan
Time: (The time axis is
101st scan
based on the CPU No.1.)
102nd scan
:
Data change when the CPU module unit guarantee
is disabled
Device memory
(Scan)
First scan
Second scan
Third scan
:
10th scan
11th scan
:
50th scan
51st scan
:
100th scan
Time: (The time axis is
101st scan
based on the CPU No.1.)
102nd scan
:
The CPU reflects (refreshes) the data in the END processing of each scan.
CPU No.2
Scan time: 10ms
CPU buffer memory
0→1
0
0
The CPU module unit guarantee is
0
enabled:
0
(5) The CPU No.2 does not update
0
(refresh) the data in the END
processing until the CPU No.3 and
4 receive the data.
Device
D0,D1
0→1 0→1
0 0
0 0
0 (4) The CPU No.2 0
reflects (refreshes) the
0 0
data in the END
0 0
processing of the CPU
No.2.
(1) The data is written from the program.
DINC D0
CPU No.1
CPU buffer memory
(Value) (Scan) (Value)
1 First scan 1
2 1
Second scan
3 Third scan 1
: : :
10 1
10th scan
11 11th scan 1
: : :
50 50th scan 1
51 1
51st scan
: : :
100 100th scan 1
101 101
101st scan
102 102nd scan 101
: : :
CPU buffer memory
(Value) (Scan) (Value)
1 First scan 1
2 Second scan 2
3 3
Third scan
: : :
10 10
10th scan
11 11th scan 11
: : :
50 50th scan 50
51 51st scan 51
: : :
100 100th scan 100
101 101
101st scan
102 102nd scan 102
: : :
CPU No.3
Scan time: 50ms
CPU buffer memory
The CPU module unit guarantee is
enabled:
(7) The CPU No.3 does not update
(refresh) the data in the END
processing until the CPU No.4
receives the data.
Device
D0,D1
0→1
0
0
0
(6) The CPU No.3 reflects (8) The CPU No.4 reflects
0
(refreshes) the data in the (refreshes) the data in the
END processing of the END processing of the
0
CPU No.3. CPU No.4.
CPU No.2 CPU No.3
Device memory Device memory
(Scan) (Value) (Scan)
1
First scan
First scan
Device memory Device memory
(Scan) (Value) (Scan)
10
First scan
Fifth scan 50 First scan
10th scan 100 Second scan
16 MULTIPLE CPU SYSTEM FUNCTION
16.4 Data Communication Between CPU Modules
CPU No.4
Scan time: 100ms
CPU buffer memory
Device
D0,D1
0→1
0
0
0
0
0
CPU No.4
Device memory
(Value) (Scan) (Value)
1
First scan 1
Device memory
(Value) (Scan) (Value)
50
100 First scan 100
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