Mitsubishi Electric MELSEC iQ-R-R00CPU User Manual page 316

■When accessing fixed scan communication area
When accessing within the multiple CPU synchronous interrupt program (I45), enabling the setting of module-by-module data
guarantee eliminates the need of an interlock circuit. When this refresh area is accessed within a program other than the
above, or when the setting of module-by-module data guarantee is disabled, an interlock circuit is required, as with the access
to the CPU buffer memory. ( Page 303 Module-by-module data guarantee)
The program reads data by transferring it in the order that it is written to the CPU buffer memory (fixed scan communication
area). Data inconsistency can be prevented by using devices written after the transfer data for interlocks, regardless of the
device type or address.
Ex.
Interlock program in communication by direct access (when accessing fixed scan communication area)
• Program example
Write
instruction
U3E0\ U3E1\
M0 HG10.0 HG0.0
(6)
U3E0\ U3E1\
HG10.0 HG0.0
(1) CPU No.1 creates send data.
(2) CPU No.1 turns on the data setting complete bit.
[Data transfer with multiple CPU communication cycle]
(3) CPU No.2 detects send data setting complete.
(4) CPU No.2 performs receive data processing.
(5) CPU No.2 turns on receive data processing complete.
[Data transfer with multiple CPU communication cycle]
(6) CPU No.1 detects receive data processing complete, and turns off the data setting complete bit.
[Data transfer with multiple CPU communication cycle]
(7) CPU No.2 detects that send data setting complete is turned off, and turns off receive data processing complete.
Also, with instructions such as BMOV instructions that involve writing data with two or more words to the CPU buffer memory,
data is written from the end address to the start address. If combining and writing send data with interlock signals with a single
instruction, data inconsistency can be prevented with an interlock signal at the start of the data.
16 MULTIPLE CPU SYSTEM FUNCTION
314
16.4 Data Communication Between CPU Modules
Send program (CPU No.1)
(3)
U3E0\
(1) HG10.0
Set send data for user
setting areas
(U3E0\HG0 to
U3E0\HG9).
(2) U3E0\
SET HG10.0
(7)
U3E0\
HG10.0
U3E0\
RST HG10.0
RST M0
Receive program (CPU No.2)
U3E1\
HG0.0 (4)
Operation using
receive data
(U3E0\HG0 to
U3E0\HG9)
(5)
U3E1\
SET HG0.0
U3E1\
HG0.0
U3E1\
SET HG0.0