Mitsubishi Electric MELSEC iQ-R-R00CPU User Manual page 348

Melsec iq-r series cpu module application user's manual
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■Precautions about counter reset
When executing the RST C instruction, the coil for C is also turned off. If the execution condition for the OUT C
instruction is turned on after the RST C instruction is executed, the coil of C is turned on and the current value is updated
(count value +1) when the OUT C instruction is executed.
M0
C0
In the above ladder example, the coil of C0 is turned on by turning off and on M0 and as a result the current value is updated.
When C0 count reaches its upper limit, C0 contact is turned on and C0 current value is cleared by execution of the RST C0
instruction. At this time C0 coil is also turned off. When M0 is turned on at the next scanning, the current value is updated
because C0 coil is turned off and on during the OUT C0 instruction execution (the current value is changed to 1).
Program
ON
M0
OFF
Coil of C0
OFF
RST C0
OFF
(1) The current value update contact turns on.
(2) The current value is updated because the coil of C0 turns on.
(3) The count value is cleared, and the contact turns off.
To address the above problem, insert a normally closed contact of the execution condition for the OUT C0 instruction into the
execution condition for the RST C0 instruction to prevent C0 coil from being turned off while the execution condition (M0) of
the OUT C0 instruction is turned on as shown in the following ladder example.
M0
C0
M0
Maximum counting speed for counters
Counting is possible only when on/off time of the input condition is longer than the execution interval of the same OUT C
instruction. Maximum counting speed for counters can be obtained by the following equation:
Maximum counting
=
speed Cmax
*1 Duty (n) is a value which expresses the ratio of on/off time of the count input signal as a percent (%) value.
Count input signal
OFF
21 DEVICES
346
21.3 User Device
K10
C0
RST
C0
END
OUT C0
RST C0
ON
(1)
The coil of C0 turns off.
(3)
K10
C0
RST
C0
n
1
×
[times/s]
100
T
T1
ON
END
OUT C0
RST C0
(2)
T2
END
• When T1≥T2, n =
T1+T2
• When T1<T2, n =
T1+T2
T2
× 100%
T1
× 100%

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