Mitsubishi Electric MELSEC iQ-R-R00CPU User Manual page 86

Multiple interrupt execution sequence
When multiple interrupts occur, the interrupt program with the highest priority is executed. Then, the interrupt program with the
highest priority among those interrupted and in waiting status as a result of interrupts will be executed next when the previous
is finished.
Ex.
Order of interrupt occurrence: 
Order of interrupt execution: 
Order of interrupt completion: 
Priority
High 1

2

3
Low
4
5
6
7
8
[Priority 5]
1) I101 interrupt program
[Priority 6]
2) I0 interrupt program
[Priority 6]
3) I150 interrupt program
[Priority 6]
4) I100 interrupt program
[Priority 7]
5) I1020 interrupt program
[Priority 8]
6) I2 interrupt program
Scan execution type program
(1) Interrupt is enabled.
(2) I50 is executed because its interrupt priority is higher.
(3) Enters waiting status because its interrupt priority is lower.
(4) I101 is executed because its interrupt priority is higher.
(5) Return from interrupt. Execution of the interrupted I50 resumes.
(6) Enters the waiting status until the execution of I50 completes because its interrupt priority is the same as that of I50 by setting.
(7) I0 is executed before I100 because its interrupt pointer is smaller.
(8) Return from interrupt. I1020 is executed because its interrupt priority is higher than those of I1020 and I0.
(9) Return from interrupt. I1020 is executed because its interrupt priority is higher than that of I2.
(10)Return from interrupt. Execution of the interrupted I2 resumes.
1 RUNNING A PROGRAM
84
1.7 Interrupt Program
Interrupt pointer
I49
I48
I44, I45
I28, I29, I30, I31
I101
I0, I50, I100
I1020
An interrupt pointer among I50 to I1023 with the priority other than 5 to 7
6) 3) 5)
(4)
(2)
EI
(1)
Time
1) 4) 2) (5)
(6)
(8)
(3)
(7)
(9)
(10)