Mitsubishi Electric MELSEC iQ-R-R00CPU User Manual page 85

Disabling/enabling interrupts with a specified or lower priority
Interrupts with a priority equal or lower than that specified by the DI or EI instruction can be disabled or enabled even when
multiple interrupts are present.
Ex.
Order of interrupt occurrence: 
Order of interrupt execution: 
Order of interrupt completion: 
Priority Interrupt pointer
High 1 I49

2 I48

3 I44, I45
Low
4 I28, I29, I30, I31
5 I101
6 I0, I50, I100
7 I1020
8 An interrupt pointer among I50 to I1023 with the priority other than 5 to 7
[Priority 2]
1) I48 interrupt program
[Priority 4]
2) I28 interrupt program
[Priority 8]
3) I10 interrupt program
Scan execution type program
Time
(1) Interrupt is enabled.
(2) Interrupts with priority 3 to 8 are disabled.
(3) I28 is not executed because interrupts with priority 3 to 8 are disabled.
(4) I48 is executed because it is a higher-priority interrupt.
(5) Return from interrupt. Execution of the interrupted I10 resumes.
(6) High-priority interrupt I28 is executed because interrupts with priority 3 to 8 have been enabled.
Disabled interrupt priorities and the current interrupt priority can be checked in SD758 (Interrupt disabling for
each priority setting value) and SD757 (Current interrupt priority) respectively.
(4)
(3)
[ DI K3 ]
[ EI ]
(1)
(5)
[ EI ]
(2)
(6)
(5)
1 RUNNING A PROGRAM
1.7 Interrupt Program
1
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