Mitsubishi Electric MELSEC iQ-R-R00CPU User Manual page 859

No. Name
SD792 PID limit setting (for
and complete derivative)
SD793
SD794 PID limit setting (for
and incomplete derivative)
SD795
SD796 Maximum number of
blocks used for the
multiple CPU
dedicated instruction
(for CPU No.1)
SD797 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.2)
SD798 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.3)
SD799 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.4)
SD816 Basic period
SD817
SD818 Bumpless function
availability setting for
the S.PIDP instruction
SD820 Dummy device
SD821
*1 When the value out of the range is specified, operation runs while its value is being regarded as max value of each range of multiple
CPU system configuration.
*2 There are restrictions on the firmware version of the supported CPU module and software version of the engineering tool. ( Page
1008 Added and Enhanced Functions)
Data stored Details
0: Limit restriction The limit restriction for each PID loop is specified as follows: (for
applied the PIDCONT instruction)
1: No limit restriction
SD792
SD793
1 to 32: Loop 1 to 32
0: Limit restriction The limit restriction for each PID loop is specified as follows: (for
applied the S.PIDCONT instruction)
1: No limit restriction
SD794
SD795
1 to 32: Loop 1 to 32
The maximum • The maximum number of blocks used for the multiple CPU
number of blocks to dedicated instruction is specified (for CPU No.1).
be used for the • When executing the multiple CPU dedicated instruction on CPU
dedicated instruction No. 1, if the number of free blocks in the dedicated instruction
Depending on the transfer area is less than the setting value on this register,
number of CPU SM796 is turned on.
modules which • This value is used as interlock signal for the continuous
constitute a multiple executions of the multiple CPU dedicated instruction.
CPU system, the
• The maximum number of blocks used for the multiple CPU
*1
range is as follows.
dedicated instruction is specified (for CPU No.2).
When constituting two
• When executing the multiple CPU dedicated instruction on CPU
modules: 2 to 599
No. 2, if the number of free blocks in the dedicated instruction
When constituting
transfer area is less than the setting value on this register,
three modules: 2 to
SM797 is turned on.
299
• This value is used as interlock signal for the continuous
When constituting
executions of the multiple CPU dedicated instruction.
four modules: 2 to
• The maximum number of blocks used for the multiple CPU
199
dedicated instruction is specified (for CPU No.3).
(Default: 2).
• When executing the multiple CPU dedicated instruction on CPU
No. 3, if the number of free blocks in the dedicated instruction
transfer area is less than the setting value on this register,
SM798 is turned on.
• This value is used as interlock signal for the continuous
executions of the multiple CPU dedicated instruction.
• The maximum number of blocks used for the multiple CPU
dedicated instruction is specified (for CPU No.4).
• When executing the multiple CPU dedicated instruction on CPU
No. 4, if the number of free blocks in the dedicated instruction
transfer area is less than the setting value on this register,
SM799 is turned on.
• This value is used as interlock signal for the continuous
executions of the multiple CPU dedicated instruction.
Execution cycle An execution cycle (unit: second) of process control instructions is
set in real number.
0: Enabled The availability of the bumpless function for the S.PIDP instruction
1: Disabled is set.
Dummy device A dummy device used in process control instructions is set.
b15 b1
16 to 2
32 to 18 17
b15 b1 b0
16 to 2 1
32 18 17
to
Appendix 5 List of Special Register Areas
Set by
(setting
timing)
U
b0
1
U
U
U
U
U
U
U
U
APPX
CPU
ALL
ALL
*2
Rn
RnP
RnSF
*2
Rn
RnP
RnSF
*2
Rn
A
RnP
RnSF
*2
Rn
RnP
RnSF
RnP
RnPSF
RnP
RnPSF
RnP
RnPSF
RnP
RnPSF
RnP
RnPSF
857