Mitsubishi Electric MELSEC iQ-R-R00CPU User Manual page 856

Melsec iq-r series cpu module application user's manual
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No.
Name
SD622
Data memory (drive
4) capacity
SD623
SD626
Extended SRAM
cassette capacity
identification
information
SD629
Program memory
write (transfer) status
SD630
Program memory
write count index
SD631
SD633
Data memory write
(transfer) status
SD634
Index for the number
of data memory write
SD635
operations
SD638
Index for the number
of system memory
write operations
SD639
SD640
Internal buffer empty
area usage status
SD642
Internal buffer
capacity
SD643
APPX
854
Appendix 5 List of Special Register Areas
Data stored
Details
Data memory (drive
The capacity of the data memory is stored in increments of 1K byte
4) capacity: the lower
(the amount of free space for a formatted memory card is stored).
digits (unit: K bytes)
Data memory (drive
The capacity of the data memory is stored in increments of 1K byte
4) capacity: the higher
(the amount of free space for a formatted memory card is stored).
digits (unit: K bytes)
Capacity identification
Capacity identification information of the Extended SRAM cassette
information of the
is stored.
Extended SRAM
Unmounted: 0, 1M: 1, 2M: 2, 4M: 3, 8M: 4, 16M: 5
cassette
Write (transfer) status
This register displays write (transfer) status to the program memory
display
in percentage (0 to 100%). The initial value is "0". Upon completion
(percent)
of writing, this register is set to "100". It is set to "0" at the time
when the write command is issued.
Index of the number
• This register indicates the index value for the number of write
of write operations up
operations to the program memory up to now (stored as a 32-bit
to now
BIN value). However, the number of write operations is not equal
to the index value.
• When the index value exceeds 100000, an error is generated
(the index value is continued to be counted even when it exceeds
100000). If the index value exceeds 100000, the CPU module
must be replaced.
Write (transfer) status
This register displays write (transfer) status to the data memory in
display
percentage. (0 to 100%). The initial value is "0". Upon completion of
(percent)
writing, this register is set to "100". It is set to "0" at the time when
the write command is issued.
Index of the number
• This register indicates the index value for the number of write
of write operations up
operations to the data memory up to now (stored as a 32-bit BIN
to now
value). However, the number of write operations is not equal to
the index value.
• When the index value exceeds 100000, an error is generated
(the index value is continued to be counted even when it exceeds
100000). If the index value exceeds 100000, the CPU module
must be replaced.
Index of the number
• This register indicates the index value for the number of write
of write operations up
operations to the system memory (Flash ROM)
to now
(stored as a 32-bit BIN value). However, the number of write
operations is not equal to the index value.
• When the index value exceeds 100000, an error is generated
(the index value is continued to be counted even when it exceeds
100000). If the index value exceeds 100000, the CPU module
must be replaced.
Internal buffer empty
This register stores the following in a bit pattern: usage status of the
area usage status
internal buffer for functions where the internal buffer capacity is not
(usage status of the
set in the internal buffer capacity setting of the CPU parameters.
internal buffer for
(On indicates being used.)
functions where the
b0: Used for realtime monitor
internal buffer
b1 to b15: Not used
capacity is not set in
the internal buffer
capacity setting of the
CPU parameters)
Internal buffer
The capacity of the internal buffer is stored in K bytes.
capacity
Low-order (in K
bytes)
Internal buffer
The capacity of the internal buffer is stored in K bytes.
capacity
High-order (in K
bytes)
*2
*3
up to now.
Set by
CPU
(setting
timing)
S (Initial)
ALL
S (Initial)
ALL
*5
S (Initial)
ALL
S (Writing)
ALL
S (Writing)
ALL
ALL
S (Writing)
ALL
S (Writing)
ALL
ALL
S (Writing)
RnPSF
RnSF
RnPSF
RnSF
S (Status
Rn
change)
S (Initial)
Rn
S (Initial)
Rn

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