Mitsubishi Electric MELSEC iQ-R-R00CPU User Manual page 861

Melsec iq-r series cpu module application user's manual
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No.
Name
SD923
Previous firmware update
*2
information (CPU)
SD924
SD925
SD926
SD927
SD928
SD929
SD930
SD931
SD932
Previous firmware update
result
SD933
*1 The CPU module where this function can be used supports these special register areas.
*2 For the RnENCPU, information of the CPU part is displayed.
Data stored
History
Execution time
information
(year)
Execution time
(month)
Execution time
(day)
Execution time
(hour)
Execution time
(minute)
Execution time
(second)
Execution time (day
of the week)
Version after the
update (CPU)
Version before the
update (CPU)
Target
Execution result
Details
The year value (four digits) of the date/time
when the firmware update was executed is
stored as a BIN code.
The month value of the date/time when the
firmware update was executed is stored as a
BIN code.
The day value of the date/time when the
firmware update was executed is stored as a
BIN code.
The hour value of the date/time when the
firmware update was executed is stored as a
BIN code.
The minute value of the date/time when the
firmware update was executed is stored as a
BIN code.
The second value of the date/time when the
firmware update was executed is stored as a
BIN code.
The day of the week value of the date/time
when the firmware update was executed is
stored as a BIN code. (0: Sun, 1: Mon, 2: Tue,
3: Wed, 4: Thu, 5: Fri, 6: Sat)
The firmware version after the update
execution is stored.
When the update is completed with an error, 0
is stored.
The firmware version before the update
execution is stored.
The start I/O number of the module where the
firmware update was executed is stored.
• CPU module: 3FFH
The execution result of the firmware update is
stored.
• 0001H: Completed successfully
• 0100H: Flash ROM error
• 0200H: Model mismatched
• 0201H: File invalid
• 0202H: Combination invalid
• 0203H: Firmware update prohibited state
• 0300H: Firmware data error
Appendix 5 List of Special Register Areas
Set by
CPU
(setting
timing)
*1
S (Initial)
Rn
*1
S (Initial)
Rn
*1
S (Initial)
Rn
*1
S (Initial)
Rn
*1
S (Initial)
Rn
*1
S (Initial)
Rn
*1
S (Initial)
Rn
*1
S (Initial)
Rn
*1
S (Initial)
Rn
*1
S (Initial)
Rn
*1
S (Initial)
Rn
APPX
859
A

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