Mitsubishi Electric MELSEC iQ-R-R00CPU User Manual page 71

Melsec iq-r series cpu module application user's manual
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■If an interrupt factor occurs while interrupt is disabled (DI)
• For I0 to I15, I28 to I31, I48, I49, and I50 to I1023
The interrupt factor that has occurred is memorized, and the interrupt program corresponding to the factor will be executed
when the interrupt is enabled. Even if the same interrupt factor occurs multiple times, it will be memorized only once. If the
IMASK instruction and SIMASK instruction are used to disable the interrupt, all the memorized factors will be discarded.
Main routine program
High
I49 interrupt program
I28 interrupt program
Low
(1) The second and following interrupt factors that occur while interrupts have been disabled (DI) are not memorized.
(2) When interrupts are enabled, interrupts are executed in order from I49 because it has a higher priority.
(3) I28 is executed. (I49 is not executed for the second time.)
• For I45
The interrupt factor that has occurred is memorized, and the I45 interrupt program will be executed when the interrupt is
enabled. Even if the I45 interrupt occurs multiple times, its interrupt factor will be memorized only once. If the IMASK
instruction and SIMASK instruction are used to disable the interrupt, all the memorized factors will be discarded.
Main routine program
I45 interrupt program
Mc: Multiple CPU synchronization cycle
(1) The interrupt factor is memorized.
(2) The second and following interrupt factors that occur while interrupts have been disabled (DI) are not memorized.
(3) The interrupt is executed.
(4) The interrupt is executed because interrupts are enabled.
Interrupts are disabled.
(DI)
I28
I49
I28
I49
×
×
(2)
(1)
I45
I45
Mc
Mc
Interrupts are disabled (DI).
(3)
EI execution
Interrupts are enabled.
(EI)
(1)
(3)
(2)
I45
Mc
Mc
(4)
t
t
1 RUNNING A PROGRAM
1.7 Interrupt Program
1
69

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