Sfc Information - Mitsubishi Electric MELSEC iQ-R-R00CPU User Manual

SFC information

The following is the special register area relating to SFC information.
No. Name
SD329 Online change (SFC
block) target block
number
*1 There are restrictions on the firmware version of the supported CPU module and software version of the engineering tool. ( Page
1008 Added and Enhanced Functions)
System clock
The following is the list of special register areas relating to the system clock.
No. Name
SD412 One second counter
SD414 2n second clock
setting
SD415 2n ms clock setting
SD420 Scan counter
Fixed scan function information
The following is the list of special register areas relating to the fixed scan function information.
No. Name
SD480 Number of cycle
overrun events for
inter-module
synchronization cycle
program (I44)
SD481 Number of cycle
overrun events for
multiple CPU
synchronization
program (I45)
SD484 Number of execution
section excess errors
for multiple CPU
synchronization
interrupt program
APPX
850
Appendix 5 List of Special Register Areas
Data stored Details
SFC block number • A target SFC block number is stored while the online change (SFC
block) is being executed (SM329 = ON).
• FFFFH is stored when the online change (SFC block) is not executed.
Data stored Details
The number of counts • The value in this register increments by one for each second
that is counted once after the CPU module enters in RUN mode.
per second. • A counting cycle from 0 to 65535 to 0 is repeated.
Unit setting for 2n • The n value of the 2n second clock is stored (Default: 30).
second clock • Configurable range is -32768 to 32767 (0 to FFFFH).
Unit setting for 2n ms • The n value for the 2n ms clock is stored. (Default: 30).
clock • Configurable range is -32768 to 32767 (0 to FFFFH).
The number of counts • The value in this register increments by one for each scan after
that is counted once the CPU module enters in RUN mode (however, the count is
for each scan. skipped for scans by the initial execution type program).
• A counting cycle from 0 to 65535 to 0 is repeated.
Data stored Details
0: No cycle overrun The number of events in which the inter-module synchronous
event interrupt program (I44) has not been completed within the inter-
1 to 65535: module synchronization cycle or the program cannot be executed
Accumulated due to various reasons, such as execution of a higher-priority
number of cycle interrupt program and interrupt disabling by the instruction
overrun events execution is stored. When the count exceeds 65535, it returns to 0
and starts a new cycle. The number of cycle overrun events is
counted regardless of the setting content for the error check setting
of the RAS setting (execution check of the inter-module
synchronous interrupt (I44)).
0: No cycle overrun The number of events in which the multiple CPU synchronization
event program (I45) has not been completed within the fixed scan
1 to 65535: communication cycle or the program cannot be executed due to
Accumulated various reasons, such as execution of a higher-priority interrupt
number of cycle program and interrupt disabling by the instruction execution is
overrun events stored. When the count exceeds 65535, it returns to 0 and starts a
new cycle. The number of cycle overrun events is counted
regardless of the setting content for the error check setting of the
RAS setting (execution check of the multiple CPU synchronization
program (I45)).
0: No error (Normal) The number of events in which the program is executed exceeding
1 to 65535: the program execution section within the specified multiple CPU
Accumulated synchronization cycle is stored. When the count exceeds 65535, it
number of errors returns to 0 and starts a new cycle. Note that the number of error
occurrences is counted regardless of the CPU module operation
setting for error detections within the RAS setting of the CPU
parameter.
Set by CPU
(setting
timing)
*1
S (Status Rn
change)
Set by CPU
(setting
timing)
S (Status ALL
change)
U ALL
U ALL
S (Every END) ALL
Set by CPU
(setting
timing)
S (Status Rn
change) RnP
*1
S (Status Rn
change) RnP
RnSF
*1
S (Status Rn
change) RnP
RnSF