Figure 48. Packet Processor Block Diagram - Alcatel 1850 TSS-320 Technical Handbook

ETH MAC processing Sk
MAC validity check
Pause frame reception
Metering on port base
Flow control
according to IEEE standard 802.3
ETH MAC processing So
MAC generation
Pause frames generation
Back pressure So process
metering on port base
according to IEEE standard 802.3
Packet processor
Packet processing in 16XGE PACKET MODULE boards is managed in order to provide following ports
management:
– MAC port
– Virtual bridge port
– Provider bridge port
– ETS port
– MPLS port
Moreover interworking between ETS/MPLS and Provider Bridge/ETS is also managed.
In Figure 48. in page 90 the functional block diagram of the packet processor.
Ethernet
Ethernet
Physical
Physical
term ination
term ination
Alcatel 1850 TSS-320 Rel. 1.1
90/270 8DG 07734 AAAA Edition 01
M AC
M AC
port
port
Virtual
Virtual
Bridge
Bridge
port
port
Provider
Provider
Bridge
Bridge
port
port
Ethernet to
Ethernet to
Provider
Provider
Bridge
Bridge
ETS
ETS
port
port
16G E PACKET MO DULE

Figure 48. Packet Processor block diagram

M AC M AC
M AC M AC
VLAN VLAN
VLAN VLAN
Provider
Provider
SVLAN SVLAN
SVLAN SVLAN Bridge to
Bridge to
Ethernet
Ethernet
ETS ETS
ETS ETS
Logical
Packet
16G E PACKET MO DULE
Switch
Ethernet
Ethernet
M AC
M AC
Physical
Physical
port
port
term ination
term ination
Virtual
Virtual
Bridge
Bridge
port
port
Provider
Provider
Bridge
Bridge
port
port
ETS
ETS
port
port
Technical Handbook Common
Functional Description