Data Processing Blocks; Figure 47. 16Xge Packet Module Block Diagram - Alcatel 1850 TSS-320 Technical Handbook

3.4.5 Data processing blocks

3.4.5.1 16XGE PACKET MODULE card
Not available in current release
16XGE PACKET MODULE boards manage incoming Ethernet traffic (either GE or FE) providing
collection of customer traffic.
Packet processing is performed on VLAN base, thus providing Ethernet Bridging (MAC) 802.1d), Virtual
Bridging (802.1q) Ethernet provider bridging (802.1ad) functionalities, in the so called 'promisquous'
mode, with no frame discarding.
Input/output scheduling functionalities are as well implemented, for RX and TX client signals respectively,
in order to manage efficiently the packet switching (see 3.4.5.2.2 on page 97).
In addition 16XGE PACKET MODULE boards are able to manage access/collection of customer traffic
(UNI interfaces) aggregated in MPLS pipes (PW LSPs or TUNNELs) in cooperation with 20G PACKET
PROCESSOR boards.
Figure 47. on page 89 represents the block diagram for 16XGE PACKET MODULE board.
ETY Sk
Recovers data from line encoded signal
detects LOS
ETY So
Condition data for line transmission
ALS management
Technical Handbook Common
Functional Description
Universal Matrix board
switch
Traffic
Manager Sk
PKT
Proc Sk
ETH
MAC proc Sk
ETY
ETY
Sk
Sk ETY
Sk
Packet Module

Figure 47. 16XGE PACKET MODULE block diagram

PKT
Traffic
Manager So
PKT
Proc So
ETH
MAC proc So
ETY
ETY
Sk
So ETY
So
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