Alcatel 1850 TSS-320 Technical Handbook page 8

Figure 53. Three steps for scheduling ..............................................................................................
Figure 54. Controller sub-system general architecture .....................................................................
Figure 55. Data Board Generic Control Architecture ........................................................................ 100
Figure 56. Equipment controller board (EC320) ............................................................................... 102
Figure 57. Matrix Board (MT320) with SLC Logic............................................................................. 104
Figure 58. Card_in architecture (Electronic Shelf) ............................................................................ 105
Figure 59. Typical Data Board with LDC controller ........................................................................... 107
Figure 60. Control interfaces............................................................................................................. 109
Figure 61. EPS architecture: Matrix failures ..................................................................................... 113
Figure 62. EPS architecture: LOA failures ........................................................................................ 113
Figure 63. Typical ring network with SNCP....................................................................................... 115
Figure 64. Failure examples in SNCP ring........................................................................................ 116
Figure 65. Drop and Continue D/C A INS A...................................................................................... 118
Figure 66. Drop and Continue D/C A INS B...................................................................................... 118
Figure 67. Drop and Continue........................................................................................................... 119
Figure 68. Drop and Continue - 1st failure........................................................................................ 120
Figure 69. Drop and Continue - 2nd failure....................................................................................... 120
Figure 70. Collapsed single node ring interconnection ..................................................................... 121
Figure 71. Collapsed single node ring interconnection -1st failure ................................................... 122
Figure 72. Collapsed single node ring interconnection -2nd failure .................................................. 123
Figure 73. 2F MS SPRING Connection ............................................................................................ 125
Figure 74. Effect of a BRIDGE "B side" operation ............................................................................ 126
Figure 75. Effect of a BRIDGE "A side" operation ............................................................................ 126
Figure 76. Effect of SWITCH "B side" operation ............................................................................... 127
Figure 77. Effect of SWITCH "A side" operation ............................................................................... 127
Figure 78. Line break recovering operations .................................................................................... 128
Figure 79. 2F MS-SPRING example of operation............................................................................. 130
Figure 80. Squelching on isolated Node connection......................................................................... 131
Figure 81. MS SPRING Drop and Continue, Insert Continues (protected)....................................... 132
Figure 82. Synchronization main processes ..................................................................................... 133
Figure 83. CRG functional view ........................................................................................................ 134
Figure 84. Output timing reference configuration.............................................................................. 135
Figure 85. Clock architecture overview............................................................................................. 138
Figure 86. ECC Intra-Shelf Architecture ........................................................................................... 140
Figure 87. AUX handling Intra-shelf Architecture.............................................................................. 141
Figure 88. Battery distribution in the rack ........................................................................................ 142
Figure 89. Main battery distribution inside framework and shelves .................................................. 143
Figure 90. Service power distribution................................................................................................ 144
Figure 91. SDH multiplexing structure and AU-3/TU-3 conversion................................................... 145
Figure 92. VC-12 Structure (asynchronous mapping of 2048 Kbit/s)................................................ 146
Figure 93. TU-12 Structure ............................................................................................................... 147
Figure 94. VC-3 structure.................................................................................................................. 148
Figure 95. TU-3 structure.................................................................................................................. 148
Figure 96. VC-4 Structure and POH byte contents ........................................................................... 149
Figure 97. STM-1 structure and SOH byte contents ......................................................................... 150
Figure 98. STM-4 structure and SOH byte contents ......................................................................... 151
Figure 99. Structure of STM-16 and SOH bytes contents................................................................. 152
Figure 100. STM-64 structure and SOH byte contents ..................................................................... 153
Figure 101. EC320 board interface................................................................................................... 156
Figure 102. .Power supply circuit block diagram .............................................................................. 160
Figure 103. EC320 Block diagram .................................................................................................... 161
Figure 104. ISPB bus connections.................................................................................................... 163
Figure 105. Control LAN Sub-system ............................................................................................... 164
Figure 106. MT320: Control sub-system block diagram ................................................................... 165
Alcatel 1850 TSS-320 Rel. 1.1
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Technical Handbook Common
List of Figures
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