Figure 49. Packet Processor Block Diagram - Alcatel 1850 TSS-320 Technical Handbook

3.4.5.2 PACKET PROCESSOR card
PACKET PROCESSOR boards manage data traffic (i.e. FE, GE) in order to allow aggregation of customer
or provider traffic.
Packet processing is performed on ETH base.
Input/output scheduling functionalities are as well implemented, for RX and TX client signals respectively,
in order to manage efficiently the packet switching (see 3.4.5.2.2 on page 97).
In the board resides the generic functionalities needed to perform packet processing and traffic
management.
Other functionalities related to the particular technology are managed in dedicated plug in modules.
Figure 49. on page 93 shows the functional block diagram for the PACKET PROCESSOR board: as an
example, the board is equipped with an ETH PIM and a multiservice PIM.
PIMs may vary depending on the application.
PIM
(e.g.
multiser
vice )
Paket processor Sk
See section 3.4.5.1 on page 89 for detailed process description.
Packet processor So
See section 3.4.5.1 on page 89 for detailed process description.
Traffic manager Sk
See section 3.4.5.1 on page 89 for detailed process description.
Traffic manager So
See section 3.4.5.1 on page 89 for detailed process description.
Technical Handbook Common
Functional Description
Universal Matrix board
PKT
switch
PACKET
Traffic
manager
PROCESSOR
PKT
proc
PIM
(e.g. ETH)

Figure 49. PACKET PROCESSOR block diagram

TDM
switch
Traffic
PIM
manager
(e.g.
multiser
PKT
vice)
proc
PIM
(e.g. ETH)
Alcatel 1850 TSS-320 Rel. 1.1
8DG 07734 AAAA Edition 01 93/270