Figure 111. Universal Matrix (Mt320) Unit Block Diagram - Alcatel 1850 TSS-320 Technical Handbook

Reset
mUSM
debug
RJ45
debug
RJ45
2xQ3
DS LAN
RJ45
2xDrop
Shelf
ISPB
ISPB
I2C
SPI bus
extension
Unit
Failure
VC 1.2V
VC 1.5V
VC 2.5V
VC 3.3V
Step-down
VC 1.8V
converters
VC 2.5V

Figure 111. UNIVERSAL MATRIX (MT320) unit block diagram

Alcatel 1850 TSS-320 Rel. 1.1
170/270 8DG 07734 AAAA Edition 01
Slot Id.
& FPGA
SPI Master
Download
HW Config.
SLC
PCI
ISPB
I2C
ETH LAN
GETH
Switch
SPI
Protection
manager
Central Scheduler
&
OH manager
SPI
Remote
Inventory
SPIDER
Alarms
DC/DC
Protection and
&
Battery Filters
Board Id
HW Config.
Performance
Monitoring
&
ISPB master
Q3 LAN
Switch
GE ILAN
HW Config.
Synchronization
10MHz
OSC
ISPB
T0
HO Matrix
ISPB
LO Matrix
ISPB (Daughter board)
SPI Slave (from other MT320)
SPI Master
Buffer
Service
VC 3.3
Voltage
Prot. Filter
UNIVERSAL MATRIX (MT320)
Shelf Id
Slot Id.
ISPB a
ISPB b
ISPB c
from to EC
5 Eth.
ILAN 32
LAN
(from to EC)
CRU
T1/T2 (port)
Timing &
(SETS)
T3a/T6a
T3b/T6b
SETG
T4a/T5a
T4b/T5b
MFSY
CK38
1
128
1
24
SPI Access Shelf
SPI WDM
SPI Master
VServ. A/B
VBatt. A/B
Technical Handbook Common
Unit Descriptions