Alcatel 1850 TSS-320 Technical Handbook page 138

3.7.1.3 T0 filtering: characteristics and operating modes
The SETG function filters the selected timing reference to ensure that the generated clock (T0) is
according to the relevant ITU-T (SDH) recommendations. Furthermore SETG function must filter the step
changes in frequency caused by (hitless) changes in the reference source.
Three modes of operation of SETG function are provided:
– Free run mode: it is a temporary operating mode entered when the clock has never acquired the
lock to an external timing reference (e.g. at system startup), or has not access to the stored data
acquired during previous lock state. The SETG output timing is totally internally controlled and
determined by the internal oscillator quality having a frequency accuracy better than ±4.6ppm as
required by G.813 Opt 1.
– Locked mode (steady state): the SETG generated clock signal is controlled by the selected
external timing reference determined by the T0 selection process; the output clock is traceable to
the selected input frequency over long term and the phase difference between the input and output
is bounded. The "holdover memory" is acquired and periodically updated (acquiring holdover
memory is a temporary mode entered when coming from free run state).
– Holdover mode (steady state): SETG has lost its controlling external timing reference, and is using
stored data, acquired whilst in locked mode, to control its output; the stored "holdover value" is an
average figure obtained over a certain period of time in order to reduce the effects of any short-term
variations that might occur in the locked reference frequency during normal operations. The internal
oscillator signal is then phase corrected according to the stored data, and used as timing reference
by SETG in holdover mode. The holdover mode will guarantee an accuracy as required by G.813
Opt 1.
3.7.1.4 SSM handling and timing selection processes
STM-N and PDH references (T1 and T2 signals) can provide (Rx direction) not only the frequency
information of the corresponding timing source but also the quality of that source by way of SSM message
extracted from the line signal: SSM information when available is typically accessed by the port framer
and collected through the parallel control bus (ISPB).
Note -If an alarm is detected on any sync source, the corresponding clock signal is turned off, insuring
that the CRG will detect a bad reference. If the source is the currently selected (the active one) a switch
to another reference or to holdover will occur; vice versa if the source is not the currently selected it will
be marked as unavailable for the selection process until the alarm disappears.
In Tx direction the SSM message is set again via parallel control bus (ISPB) on any outgoing STM-N or
PDH interface.
Station input and output references carrying the SSM information (T6 and T5) are frame aligned on the
SLCCRU daughter board where received and transmitted SSM are accessed via control interface (ISPB).
The source selection can work in two distinct modes: QL-disabled (selection based on SF, Priority and
Ext Commands) and QL-enabled (selection based on Quality, SF, Priority and Ext Commands).
T0 and T4/5 selection process are independent although the implemented algorithm is the same; in a
protected configuration happens that
• There is always one T0 selection process controlling and keeping aligned SEL_B on SLCCRU
daughter board copy A and B; the selection of the internal clock from the active copy is done
at port level.
Alcatel 1850 TSS-320 Rel. 1.1
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Functional Description