Intra Shelf Synchronization Signals Distribution; Figure 85. Clock Architecture Overview - Alcatel 1850 TSS-320 Technical Handbook

3.7.2 Intra shelf synchronization signals distribution

The Clock Reference Generator (CRG) function is the core of shelf timing distribution
Figure 85. on page 138 shows the intra-shelf clock signals distribution
T3/T6 T3/T6
LIU LIU
T4/T5 T4/T5
SSM SSM
insert insert
T0_A T0_A
Matrix A Matrix A
Matrix A Matrix A
Clk 38.88Mhz Clk 38.88Mhz
plus sync pulse plus sync pulse
Alcatel 1850 TSS-320 Rel. 1.1
138/270 8DG 07734 AAAA Edition 01
PSF A PSF A
POW320
EPS Sel EPS Sel
SSM SSM
extract extract
2 x 2M/1.5M 2 x 2M/1.5M
Str 3E Str 3E
6 x T1 6 x T1
SETG SETG
G813 G813
SETG SETG
OXC OXC
Port #32 Port #32
Port #1 Port #1
N to 6 T1 selection N to 6 T1 selection
matrix matrix

Figure 85. Clock architecture overview

POW320
PSF B PSF B
T1 tri-state T1 tri-state
SSM SSM
sync bus sync bus
extract extract
6 6
2 x 2M/1.5M 2 x 2M/1.5M
Str 3E Str 3E
6 x T1 6 x T1
SETG SETG
G813 G813
SETG SETG
OXC OXC
Clk 38.88Mhz Clk 38.88Mhz
plus sync pulse plus sync pulse
T3/T6 T3/T6
EPS Sel EPS Sel
LIU LIU
T4/T5 T4/T5
SSM SSM
insert insert
T0_B T0_B
Technical Handbook Common
Functional Description