Figure 52. Scheduler Implementation - Alcatel 1850 TSS-320 Technical Handbook

ETH based traffic
MAC generation
ETH encapsulation into GFP/LAPS frames
GFP/LAPS frames generation
metering (GFP/LAPS frames)
3.4.5.2.2 Packet switch
The Packet switching functionality is implemented in the matrix board of the equipment, by means of the
payload agnostic switching device, able to switch both TDM and data traffic.
The device is able to provide switching capabilities with packet granularity, fully non blocking with respect
to any broadcast type.
See section 3.3 on page 70 for the maximum switching capacity allowed in the system.
When dealing with packet based traffic, the UNIVERSAL MATRIX device receives from data boards
(PACKET PROCESSOR and 16XGE PACKET MODULE) the data traffic to be cross connected together
with the information needed to manage the schedulers.
Traffic managers implemented in the data boards are responsible for the traffic regulation, by means of
scheduling algorithms, which determine the amount of traffic to be transmitted to the matrix device first
and then to the egress board, depending on the quality of service to be guaranteed. It is implemented a
mechanism based on the exchange of information (in terms of the so called 'requests' and 'credits')
between the ingress and egress through the matrix, in order to efficiently manage the scheduling
algorithm, which is therefore splitted into 'input scheduler', central scheduler' and 'egress scheduler', as
depicted in Figure 52. on page 97.
PIM
Input scheduler
PKT
PIM processor
DATA BOARD
PIM
Input scheduler
PKT
PIM
processor
DATA BOARD
Technical Handbook Common
Functional Description
Traffic
manager
UNIVERSAL
MATRIX
Traffic
CENTRAL
SCHEDULER
manager
MATRIX
BOARD

Figure 52. Scheduler implementation

MPLS/IP based traffic
MPLS/IP traffic encapsulation into Cisco propri-
etary HDLC/GFP/ standard PPP HDLC frames
(LAPS tbc)
GFP/Cisco proprietary HDLC/ standard PPP
HDLC frames generation (LAPS tbc)
metering (GFP/LAPS/HDLC frames)
Output scheduler
Traffic
manager
DATA BOARD
Output scheduler
Traffic
manager
DATA BOARD
Alcatel 1850 TSS-320 Rel. 1.1
8DG 07734 AAAA Edition 01
PKT
processor
PIM
PKT
processor
PIM
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