Figure 92. Vc-12 Structure (Asynchronous Mapping Of 2048 Kbit/S) - Alcatel 1850 TSS-320 Technical Handbook

8 bit
VC-12
POH of VC-12
125 us
W
J2
C1 C2o o o r r
125 us
N2
C1 C2o o o r r
125 us W
K4
C1 C2r r r r S1
S2 i i i i i i i
125 us
W
POH STRUCTURE (V5) :
- 2 BITS TO ESTIMATE THE BER THROUGH THE BIP-2
ENCODING PROCEDURE PERFORMED ON THE PREVIOUS
VIRTUAL CONTAINER (THE FIRST AND SECOND BITS OF
BIP-2 CONSTITUTE THE PARITY BIT OF ODD AND EVEN
ORDER BITS)
- 1 BIT TO INDICATE (TO THE REMOTE TERMINAL) THE
RESULT OF THE BER ESTIMATION DETECTED ON THE
OPPOSITE DIRECTION: VALUES 0 AND 1 OF BIT FEBE
(FAR END BLOCK ERROR), (actually named REI)
RESPECTIVELY INDICATE ABSENCE OF VIOLATION AND
PRESENCE OF ONE OR TWO VIOLATIONS OF THE
PARITY LIMITS ESTABLISHED BY BIP-2
- 1 BIT TO CHECK THE PATH TRACE THROUGH AN
APPROPRIATE PROTOCOL
(RFI: path Remote Failure Inication)
- 3 BITS PRESETTABLE FOR THE SIGNAL LABEL
- 1 BIT FOR THE FERF (FAR END RECEIVE FAILURE)
ALARM INDICATION (actual RDI)

Figure 92. VC-12 Structure (asynchronous mapping of 2048 Kbit/s)

Alcatel 1850 TSS-320 Rel. 1.1
146/270 8DG 07734 AAAA Edition 01
V5 = THE BYTE PROVIDES THE FUNCTIONS OF ERROR
V5
G
G = rrrrrrrr (r = BIT INTERVAL FOR FIXED JUSTIFICATION)
W
W = iiiiiiii (i = 2.048 Mbit/s TRIBUTARY BIT)
J2 =USED TO TRANSMIT REPETITIVELY A LOW ORDER PATH
32 byte
W
G
C1, C2 = JUSTIFICATION SIGNALLING BIT
o = OVERHEAD BITS
W
S1, S2 = NEGATIVE AND POSITIVE JUSTIFICATION
W
32 byte
N2 =THIS BYTE IS ALLOCATED TO PROVIDE A TANDEM
W
K4 =THIS BYTE ARE ALLOCATED FOR APS SIGNALLING
G
W
32 byte
W
G
W
31 bytes
W
G
CHECKING, SIGNAL LABEL ANDPATH STATUS OF THE VC-12
ACCESS POINT IDENTIFIER SO THAT A PATH RECEIVING
TERMINAL CAN VERIFY ITS CONTINUED CONNECTION
TO THE INTENDED TRANSMITTER. A 16-BYTE FRAME IS
DEFINED FOR THE TRANSMISSION OF PATH ACCESS
POINT IDENTIFIERS.
OPPORTUNITY REFERRED TO SIGNALLINGS C1 AND C2
CONNECTION MONITORING (TCM) FUNCTION
FOR PROTECTION AT LOWER ORDER PATH LEVEL
V5 STRUCTURE:
b1 b2 b3
R
E
BIP-2
I
N2 STRUCTURE:
b1 b2 b3
BIP-2 1
N2 STRUCTURE:
- 2 BITS ARE USED AS AN EVEN BIP-2 FOR THE
TANDEM CONNECTION
- BIT 3 IS FIXED TO 1
- BIT 4 OPERATES AS AN "INCOMING AIS" INDICATOR
- BIT 5 OPERATES AS THE TC-REI OF THE TANDEM
CONNECTION TO INDICATE ERRORED BLOCKS
CAUSED WITHIN THE TANDEM CONNECTION
- BIT 6 OPERATES AS THE OEI (OUTGOING ERROR
INDICATING) TO INDICATE ERRORED BLOCKS OF
THE EGRESSING VC-n
- BIT 7 AND 8 OPERATE IN A 76 MULTIFRAME AS:
- THE ACCESS POINT IDENTIFIER OF THE TANDEM
CONNECTION (TC-APId);
- THE TC-RDI, INDICATING TO THE FAR END THAT
DEFECT HAVE BEEEN DETECTED WITHIN THE
TANDEM CONNECTION AT THE NEAR END
TANDEM CONNECTION SINK;
- THE ODI, INDICATING TO THE FAR END THAT
TU-AIS HAS BEEN INSERTED AT THE TC-sink
INTO THE EGRESSING TU-n DUE TO DEFECT
BEFORE OR WITHIN THE TANDEM CONNECTION;
- RESERVED CAPACITY (FOR FUTURE USE)
Technical Handbook Common
b4 b5 b6 b7 b8
R
R
SIGNAL
F
D
LABEL
I
I
b4 b5 b6 b7 b8
TC-APId,
Incoming
TC-RDI,
AIS TC-REI OEI
ODI,
reserved
Functional Description