Synchronization Architecture; Shelf Synchronization; Figure 82. Synchronization Main Processes - Alcatel 1850 TSS-320 Technical Handbook

3.7 Synchronization architecture

The characteristics of the timing function are in accordance with ITU-T G.813 Option 1 (networks
optimized for the 2048Kbit/s hierarchy) and ETSI prETS 300 462-5 are the references for internal and
external clock generation.
ETSI prETS 300 417-6 and ITU-T G.781 are the reference for the basic building blocks and algorithms
determining the timing function behaviors (sync interfaces configuration, SSM management, external
commands etc.).
The equipment Clock Reference Generator (CRG) function is located in the matrix card (MT320).
The board also hosts second level controller.
The main processes by which the clock reference function is made up, are summarized in Figure 82. on
page 133.
T2 IN from PDH ifs T2 IN from PDH ifs
T1 IN from T1 IN from
SDH/ Sonet ifs SDH/ Sonet ifs
All the boards present in the system included data boards, UNIVERSAL MATRIX and LO matrix are slave
with respect to the clock and sync pulses distributed by matrix card and therefore every card must receive
those signals

3.7.1 Shelf synchronization

The equipment Clock Reference Generator (CRG) function includes an internal oscillator and two
synchronous timing generators one for the internal clock (T0) and another one for the station output clock
(T4/T5).
The active CRG, for instance CRG A, provides the internal equipment master clock (T0) to every card in
the system as output of T0 filtering process (Phase Locked Loop) which can be phase locked to different
synchronization sources as determined by T0 selection process; when no valid sync inputs are available
the CRG will run in free-running or holdover mode.
Furthermore the CRG can provide a redundant output reference clock to an external timing generator as
determined by T4/T5 selection process.
Technical Handbook Common
Functional Description
T0 selection T0 selection
T4/T5 selection T4/T5 selection
SSM processing SSM processing
T0 filtering SEC T0 filtering SEC
(SDH only) (SDH only)
1+1 EPS process 1+1 EPS process

Figure 82. Synchronization main processes

T3/T6 Ext IN ifs T3/T6 Ext IN ifs
T0 internal clk T0 internal clk
T4/T5 Ext OUT ifs T4/T5 Ext OUT ifs
T0 filtering Str 3E
(Sonet only)
Alcatel 1850 TSS-320 Rel. 1.1
8DG 07734 AAAA Edition 01 133/270