Limit Fail Register Set - Agilent Technologies 8712ET Programmer's Manual

Using Status Registers
The Analyzer's Status Register Sets

Limit Fail Register Set

The Limit Fail register set monitors limit test results for both
measurement channels.
The inputs for the bits in the Limit Fail condition register are latched.
(See Figure 5-6.) The two bits for measurement channel 1 are latched
when the Limit Test is OFF for channel 1 or when MEAS 1 is OFF. The
two bits for measurement channel 2 are latched when Limt Test is OFF
for channel 2 or when MEAS 2 is OFF.
The following conditions determine the state for each of the bits when
the corresponding Limit Test is ON.
Measurement Channel 1 Limit Failed
(bit 0) is set to 1 when limit testing is enabled and any
point on measurement channel 1 fails the limit test, or
when any enabled marker limit on measurement channel
1 has failed.
Measurement Channel 2 Limit Failed
(bit 1) is set to 1 when limit testing is enabled and any
point on measurement channel 2 fails the limit test, or
when any enabled marker limit on measurement channel
2 has failed.
Measurement Channel 1 Marker Limit Failed
(bit 2) is set to 1 when any enabled marker limit on
measurement channel 1 has failed.
Measurement Channel 2 Marker Limit Failed
(bit 3) is set to 1 when any enabled marker limit on
measurement channel 2 has failed.
5-16 Programmer's Guide