Figure 2-3 Bits Clock Source Ports On Pxm45 Ui-S3 Back Card - Cisco MGX 8850 (PXM1E/PXM45) Configuration Manual

Chapter 2 Configuring General Switch Features
When NCDP is enabled, your manual configuration is disabled, and vice versa. When you disable NCDP,
Note
your node reverts back to any manual clock configuration that was previously done on the node. If you
re-enable NCDP after disabling it, your switch will remember your last NCDP configuration and use that
unless you change it.
Both clock source options can use built-in hardware ports designed for Building Integrated Timing System
(BITS) clock sources.
Figure 2-4
The clock source ports on the PXM-UI-S3 and PXM-UI-S3/B cards can be used to receive clock signals
from either T1 or E1 lines; the card does not support both line types simultaneously. These clock ports
support stratum levels 1 to 3.
The PXM45 and PXM1E cards support T1 data (1.544Mbps) and E1 data (2.048Mbps) clock sources,
Note
and the PXM1/B supports both T1 and E1 data types and an E1 sync (2.048MHz) line as a clock input.
The E1 sync line is not supported on switches with PXM45 and PXM1E cards.
Figure 2-3
port 35
port 36
Cisco MGX 8850 (PXM1E/PXM45), Cisco MGX 8950, Cisco MGX 8830, and Cisco MGX 8880 Configuration Guide
Release 5.0.10, OL-3845-01 Rev. B0, August 16, 2004
Figure 2-3 shows how BITS clock sources connect to the PXM45 UI-S3 back card.
shows how BITS clock sources connect to the PXM1E UI-S3/B back card.
BITS Clock Source Ports on PXM45 UI-S3 Back Card
PXM
UI-S3
C
P
M
P
L
A
N
1
L
A
N
2
c
L
K
1
c
L
K
2
A
L
A
R
M
Configuring Clock Sources
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