Table of Contents
Advertisement
Introduction
LED D1 is lit indicating the presence of the 6-V supply voltage to the EVM, while LED D2 is lit indicating
the presence of the USB to serial converter power. LEDs D3 and D4 indicate the status of the ADS58H40
High Resolution Burst Mode. Table 5 lists the description of each LED indicator.
Reference
Designator
D1
D2
D3
D4
1.4
EVM ADC Input Circuit Configurations
Figure 4
shows the ADS58H40 ADC input circuit. The default setup has a dual 1:1 impedance ratio
transformer input circuit, which achieves better phase and amplitude balance of the input signal than is
typically produced by a single transformer input circuit. Third-order bandpass filter component pads are
available for installing bandpass filter components. The default components for the bandpass filter are
either zero Ω or open circuit.
The default input termination is 50 Ω, which is formed by two 25-Ω resistors connected to the ADC VCM
node. If the user chooses to use 100-Ω termination with the 1:2 impedance transformer, the optional RLR
differential arm can be used to tune the in-band flatness.
The ADC analog input consists of a switched-capacitor-based, differential sample-and-hold (S/H)
architecture. Due to the opening and closing of the sampling glitches, the kick-back noise from the S/H
circuit may affect the ADC performance. Besides the on-chip R-C filter of the ADC input, the external
RLCR circuit provides additional filtering of the glitches. The default RLCR components have been
optimized for input bandwidth centered at 185 MHz. For additional RLCR components of different center
frequencies, refer to the ADS58H40 datasheet (SBAS589).
1:1
Jp
Jn
0.1 PF
Figure 5
shows the ADS58H40 clock input circuit. The clock signal goes through the 1:4 impedance ratio
transformer increasing the clock amplitude by two (1:4 impedance ratio equals to 1:2 voltage ratio). The
two 121-Ω resistors will impedance transform back to the primary side as 50-Ω load impedance for the
signal source generator. For ADC evaluation, set the signal generator output to 10 dBm.
6
ADS58H40 EVM
Table 5. ADS58H40 EVM LED Indicators
Description
When lit, D1 shows the presence of the 6-V (main) power supply
When lit, D2 shows the presence of the USB to serial converter power
When lit, D3 indicates that the ADC is ready to enter trigger mode
When lit, D4 indicates that the ADC is in high resolution burst mode
0 :
0 :
1:1
DNI
0 :
0 :
0.1 PF
rd
3
Order Bandpass Filter
Figure 4. ADS58H40 ADC Input Circuit
CLK IN
J10
Figure 5. ADS58H40 Clock Input Circuit
Copyright © 2012, Texas Instruments Incorporated
0 :
0 :
25 :
0 :
DNI
0 :
0 :
25 :
0.1 PF
0.1 PF
RLR Circuit
0.1 PF
1:4
121 :
0.1 PF
121 :
0.1 PF
www.ti.com
10 :
25 :
V
CM
14-bit
10 pF
82 nH
ADC
25 :
10 :
RLCR Circuit
SLAU455 – August 2012
Submit Documentation Feedback
Advertisement
Table of Contents
