Ppc Write Posting - Motorola MTX Series Programmer's Reference Manual

The PPC Register File decoder determines the address location of the
Raven's PPC registers from the PPC bus. These registers may be accessed
using only 1-, 2-, 3-, 4-, or 8-byte operations. The location of the PPC
register file is fixed beginning at PPC address $FEFE0000 or $FEFF0000,
depending on the state of the EXT01 bit at the time RST* is released. If the
EXT01 pin is sampled in the low state, the PPC register file will start at
address $FEFE0000. If the EXT01 pin is sampled in the high state, the
PPC register file will start at address $FEFF0000. All references to the
PPC register file within this specification will assume a base address of
FEFF0000. All Raven registers are described in detail later in this chapter.
The Raven includes four programmable decoders which control accesses
from the PPC bus to the PCI bus. These decoders provide a window into
the PCI bus from the PPC bus. The most significant 16 bits of the PPC
address are compared with the address range of each map decoder, and if
the address falls within the specified range, the access is passed on to PCI.
For each map, there is an associated set of attributes. These attributes are
used to enable read accesses, enable write accesses, enable write posting,
and define the PCI transfer characteristics. Each map decoder also includes
a programmable 16-bit address offset. The offset is added to the 16 most
significant bits of the PPC address, and the result is used as the PCI
address. This offset allows PCI devices to reside at any PCI address,
independent of the PPC address map.
Care should be taken to assure that all programmable decoders decode
unique address ranges. Overlapping address ranges will lead to undefined
operation.

PPC Write Posting

The PPC write FIFO stores up to eight data beats in any combination of
single- and burst transactions. If write posting is enabled, Raven stores the
data necessary to complete an PPC write transfer to the PCI bus and
immediately acknowledges the transaction on the PPC bus. This frees the
PPC bus from waiting for the potentially long PCI arbitration and transfer.
The PPC bus may be used for more useful work while the Raven manages
the completion of the write posted transaction on PCI.
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Functional Description
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