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Programming Details
Table 2-2. MV64360 Power-Up Configuration Settings (continued)
2
Device
AD Bus
Signal
TxD0[7]
TxD1[1]
TxD1[4:2]
Flash Memory
Real-Time Clock and NVRAM
2-8
Default
Select
Power-Up
Option
Setting
Resistor
0
Resistor
0
Resistors
000
The MVME6100 contains two banks of flash memory accessed via the
Device Controller bus contained within MV64360. Each bank contains
from 8MB to 64MB of 32-bit wide Boot Block flash memory provided by
two 16-bit wide Intel StrataFlash devices.
The Boot Bank is jumper selectable to select either flash bank as the boot
bank. The jumper effectively swaps the chip selects to the two flash banks
so that either bank can be used as the boot bank. The state of the jumper is
readable in the BANK_SELECT bit of System Status Register 1 to
properly set up the MV64360 Device Controller Bus memory maps.
The boot device bank is the same as any of the other device banks except
that its default address map matches the PowerPC CPU boot address
(0xfff0.0100) and that its default width is sampled at reset.
The Real-Time Clock/NVRAM/Watchdog Timer is implemented using a
SGS-Thompson M48T37V Timekeeper SRAM, and M4T28-BR12SH1
SnapHat battery. Refer to the M48T37V data sheets for additional
programming information. Refer to
Description
State of Bit vs. Function
JTAG Pad
0
Calib Bypass
1
Core PLL
0
Bypass
1
Core PLL
000
Control
Appendix A, Related
Computer Group Literature Center Web Site
Normal Operation
Bypass pad calibration
Normal Operation
Bypass the core's PLL
Tuning of the core PLL
clock tree.
Documentation.
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