Dsp56F807Evm Configuration Jumpers; Block Diagram Of The Dsp56F807Evm - Motorola Digital DNA DSP56F807 Hardware User Manual

necessary for a user to write and debug software, demonstrate the functionality of that
software and interface with the customer's application-specific device(s). The
DSP56F807EVM is flexible enough to allow a user to fully exploit the DSP56F807's
features to optimize the performance of their product, as shown in
RESET
LOGIC
MODE/IRQ
LOGIC
Program Memory
64Kx16-bit
SRAM
Data Memory
64Kx16-bit
SRAM
Memory
Expansion
Connector(s)
JTAG
Connector
Parallel
DSub
JTAG
25-Pin
Interface
Low Freq
Crystal
Figure 1-1. Block Diagram of the DSP56F807EVM

1.2 DSP56F807EVM Configuration Jumpers

Seventeen jumper groups, (JG1-JG17), shown in
features on the DSP56F807EVM board.
settings.
1-2
DSP56F807
RESET SPI
MODE/IRQ SCI #0
Address,
Data &
Control
SCI #1
CAN
TIMER
GPIO
PWM #1
JTAG/OnCE
A/D #0
A/D #1
PWM #2
XTAL/EXTAL
3.3 V & GND
Table 1-1
DSP56F807EVM Hardware User's Manual
Figure
4-Channel
10-bit D/A
RS-232
Interface
Peripheral
Expansion
Connector(s)
Pri UNI-3
Sec UNI-3
Power Supply
3.3V, 5.0V & 3.3VA
Figure 1-2, are used to configure various
describes the default jumper group
1-1.
DSub
9-Pin
CAN Interface
Debug LEDs
PWM LEDs
Over V Sense
Over I Sense
Zero Crossing
Detect