Battery-Backed-Up Ram And Clock; Vmebus Interface And Vmechip2; I/O Interfaces - Motorola MVME162P2 Series Installation And Use Manual

Functional Description

Battery-Backed-Up RAM and Clock

4

VMEbus Interface and VMEchip2

I/O Interfaces

4-12
An M48T58 RAM and clock chip is used on the MVME162P2. This chip
provides a time-of-day clock, oscillator, crystal, power fail detection,
memory write protection, 8KB of RAM, and a battery in one 28-pin
package. The clock provides seconds, minutes, hours, day, date, month,
and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and
30-day months are made automatically. No interrupts are generated by the
clock. Although the M48T58 is an 8-bit device, the interface provided by
the Petra chip supports 8-, 16-, and 32-bit accesses to the M48T58. Refer
to the description of the Petra MC2 function in the MVME1X2P2 VME
Embedded Controller Programmer's Reference Guide and to the M48T58
data sheet for detailed programming guidance and battery life information.
The VMEchip2 ASIC provides the local-bus-to-VMEbus interface, the
VMEbus-to-local-bus interface, and the DMA controller functions of the
local VMEbus. The VMEchip2 also provides the VMEbus system
controller functions. Refer to the VMEchip2 description in the
MVME1X2P2 VME Embedded Controller Programmer's Reference
Guide for detailed programming information.
Note that the Abort switch logic in the VMEchip2 is not used. The GPI
inputs to the VMEchip2 which are located at $FFF40088 bits 7-0 are not
used. Instead, the Abort switch interrupt is integrated into the Petra MC2
sector at location $FFF42043. The GPI inputs are integrated into the Petra
MC2 sector at location $FFF4202C, bits 23-16.
The MVME162P2 provides onboard I/O for many system applications.
The I/O functions include serial ports, IndustryPack (IP) interfaces, and
optional interfaces for LAN Ethernet transceivers and SCSI mass storage
devices.
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