I2C Bus Management - Xilinx Virtex-7 VC7203 User Manual

I2C Bus Management

The I
Semiconductor PCA9547). The FPGA communicates with the multiplexer through I
data and clock signals mapped to FPGA pins E21 and F21, respectively. The I
the PCA9547 device is 0x70. The bus hosts four components:
•
•
•
•
•
An I
control register of the MUX as shown in
Table 1-21:
VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
2
C bus is controlled through U39, an 8-channel I
SuperClock-2 module
7 series GTX transceiver power supply module
FMC1
FMC2
FMC3
2
C component can be accessed by selecting the appropriate channel through the
2
I C Channel Assignments
U39 Channel
0 SuperClock-2 module
1 7 series GTX transceiver power supply module
2 FMC1
3 FMC2
7 FMC3
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2
C-bus multiplexer (NXP
Table 1-21.
2
I C Component
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Detailed Description
2
C
2
C idcode for
45