Omron CS1G/H-CPUxxH Instructions Manual page 372

Data Shift Instructions
Operands
Operand Specifications
Description
C: Control Word
15 12 11 8 7
C
0
Always 0.
Data shifted into register
0 Hex: 0 shifted in
8 Hex: Contents of rightmost bit shifted in
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
EM Area without bank
EM Area with bank
Indirect DM/EM
addresses in binary
Indirect DM/EM
addresses in BCD
Constants
Data Registers
Index Registers
Indirect addressing
using Index Registers
NASR(581) shifts D (the shift word) by the specified number of binary bits
(specified in C) to the right (from the rightmost bit to the leftmost bit). Either
0
No. of bits to shift: 00 to 10 Hex
D
CIO 0000 to CIO 6143
W000 to W511
H000 to H511
A448 to A959
T0000 to T4095
C0000 to C4095
D00000 to D32767
E00000 to E32767
En_00000 to En_32767
(n = 0 to C)
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
---
DR0 to DR15
---
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Section 3-9
C
A000 to A447
A448 to A959
Specified values only
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