Omron CS1G/H-CPUxxH Instructions Manual page 787

Interrupt Control Instructions
Note
Scheduled Interrupt Processing (N=4 or 5)
Scheduled Interrupt
Processing
1,2,3...
766
After completion of interrupt task 3, recorded interrupts are executed in order
of their priority. Since an input from interrupt input 0 was recorded, I/O inter-
rupt task 0 (interrupt task 100) will be executed when task 3 is completed.
Interrupt input 1 isn't retained by CLI(691), so that input is cleared.
Interrupt input 0
Interrupt input 1
Interrupt input 2
Recorded interrupts
I/O Interrupt task
If interrupt inputs 0 through 3 all go ON and CLI(691) isn't executed, all of the
inputs will be recorded and the interrupt tasks will be executed in order after
interrupt task 3 is completed. (The interrupt tasks are executed in order of
their priority, from the lowest interrupt number to the highest.)
Interrupt task 3
Interrupt task 0
Interrupt task 1
Interrupt task 2
Interrupt task 3
1. It isn't always necessary to use CLI(691).
2. When CLI(691) isn't executed, all of the I/O interrupt inputs received during
the execution of an interrupt task will be recorded. If a recorded input is re-
ceived again, the later input will be ignored.
3. When two or more I/O interrupt inputs are recorded, they are executed in
order of their priority. The order in which the recorded inputs were received
is irrelevant.
A scheduled interrupt is repeated at regular intervals set with MSKS(690) and
independent of the timing of the PLC cycle. N numbers 4 and 5 correspond to
scheduled interrupt numbers 2 and 3, respectively.
The main features of scheduled interrupt processing are listed below.
1. The scheduled interrupts are masked (disabled) when the PLC is first
turned on.
2. Set the time to the first scheduled interrupt (after execution of MSKS(690))
with CLI(691). The time to the first scheduled interrupt is unpredictable if it
isn't set with CLI(691).
Interrupt input 1 is cleared by CLI(691).
Already recorded, so
later input is ignored.
Task 3 Task 0
CLI(691) is executed. Interrupt inputs 0 and 3
are retained and input 1 is cleared.
Section 3-20
Task 3