Omron CS1G/H-CPUxxH Instructions Manual page 779

Sysmac cs series; sysmac cj series
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Interrupt Control Instructions
Description
Note
758
Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
EM Area without bank
EM Area with bank
Indirect DM/EM
addresses in binary
Indirect DM/EM
addresses in BCD
Constants
Data Registers
Index Registers
Indirect addressing
using Index Registers
Depending on the value of N, CLI(691) either clears the specified recorded I/O
interrupts or sets the time before execution of the first scheduled interrupt.
With the CJ1M, it can also be used to clear interrupts for the high-speed
counters.
N = 0 or 1 (0 to 3 for C200HS-INT01 or 6 to 9 for CJ1M CPU Unit Built-in
Interrupt Inputs)
Values 0 and 1 (0 to 3) correspond to Interrupt Input Units 0 and 1 (0 to 3).
Bits 0 to 7 of S correspond to interrupt input numbers 0 to 7 in the specified
Unit. CLI(691) clears a recorded interrupt input when the corresponding bit of
S is ON and retains the recorded interrupt input when the corresponding bit is
OFF.
Interrupt input n
Internal status
Recorded interrupt cleared
If an I/O interrupt task is being executed and an interrupt input with a different
interrupt number is received, that interrupt number is recorded internally. The
recorded I/O interrupts are executed later in order of their priority (from the
lowest number to the highest). CLI(691) can be used to clear these recorded
interrupts before they are executed.
1. MSKS(690) can be used to enable a particular I/O interrupt task in a par-
ticular cycle and disable the task in other cycles.
N
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Specified values only
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Interrupt
input n
Internal
status
Section 3-20
S
A000 to A959
T0000 to T4095
C0000 to C4095
D00000 to D32767
E00000 to E32767
En_00000 to En_32767
(n = 0 to C)
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to
@ En_32767
(n = 0 to C)
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
DR0 to DR15
,IR0 to ,IR15
–2048 to +2047, IR0 to –
2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15
Recorded interrupt retained

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