Omron CS1G/H-CPUxxH Instructions Manual page 178

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Sequence Input Instructions
3-3-9
Differentiated and Immediate Refreshing Instructions
Coding Example (2)
Instruction
LD
AND NOT
LD NOT
AND NOT
LD
AND
.
.
OR LD
OR LD
.
.
OUT
The OR LOAD instruction can be used repeatedly. In programming method
(2) above, however, the number of OR LOAD instructions becomes one less
than the number of LOAD and LOAD NOT instructions before that.
In method (2), make sure that the total number of LOAD and LOAD NOT
instructions before OR LOAD is not more than eight. To use nine or more, pro-
gram using method (1). If there are nine or more with method (2), then a pro-
gram error will occur during the program check by the Peripheral Device.
Coding
Address
000100
000101
000102
000103
000104
000105
Second LD: Used for first bit of next block connected in series to previous block.
The LOAD, AND, and OR instructions have differentiated and immediate
refreshing variations in addition to their ordinary forms, and there are also two
combinations available.
The LOAD NOT, AND NOT, OR NOT, OUT, and OUT NOT instructions have
immediate refreshing variations in addition to their ordinary forms.
The I/O timing for data handled by instructions differs for ordinary and differ-
entiated instructions, immediate refreshing instructions, and immediate
refreshing differentiated instructions.
Ordinary and differentiated instructions are executed using data input by pre-
vious I/O refresh processing, and the results are output with the next I/O pro-
cessing. Here "I/O refreshing" means the data exchanged between the CPU's
internal memory and the I/O Unit.
In addition to the above I/O refreshing, an immediate refresh instruction
exchanges data with the I/O Unit for those words that are accessed by the
instruction. An immediate refresh instruction refreshes eight bits simulta-
neously (leftmost or rightmost eight bits) in addition to the specified bit.
Operand
000000
000001
000002
000003
000004
000005
.
.
---
---
.
.
000501
Instruction
LD
AND NOT
LD
AND
OR LD
OUT
Section 3-3
Operand
000000
000001
000002
000003
---
000501
157

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