Omron CS1G/H-CPUxxH Instructions Manual page 664

Table Data Processing Instructions
Operand Specifications
Description
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
EM Area without bank
EM Area with bank
Indirect DM/EM
addresses in binary
Indirect DM/EM
addresses in BCD
Constants
Data Registers
Index Registers
Indirect addressing
using Index Registers
SRCH(181) searches the range of memory from R1 to R1+C–1 for words that
contain the comparison data (Cd). If a match is found, SRCH(181) writes the
PLC memory address of the word to IR00 and turns the Equals Flag ON.
(If there are two or more matches, just the address of the first word containing
the comparison data is written to IR00.)
When bit 15 of C+1 has been set to 1, SRCH(181) writes the number of
matches to DR00. When bit 15 of C+1 is 0, DR00 is left unchanged.
R1
R1+(C–1)
C
CIO 0000 to CIO 0000 to CIO 6143
CIO 6142
W000 to W510 W000 to W511
H000 to H510 H000 to H511
A000 to A958 A000 to A959
T0000 to T4094 T0000 to T4095
C0000 to C4094 C0000 to C4095
D00000 to D00000 to D32767
D32766
E00000 to E00000 to E32767
E32766
En_00000 to En_00000 to En_32767 (n = 0 to C)
En_32766
(n = 0 to C)
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Specified values ---
only
---
---
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
PC memory
address
Search
Cd
C
Match
Section 3-17
R1 Cd
#0000 to #FFFF
(binary)
DR0 to DR15
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