Omron CS1G/H-CPUxxH Instructions Manual page 179

Sequence Input Instructions
Instruction variation
Ordinary LD, AND, OR, LD NOT,
AND NOT, OR NOT
OUT, OUT NOT
Differentiated up @LD, @AND, @OR
Differentiated down %LD, %AND, %OR
Immediate refresh !LD, !AND, !OR, !LD NOT,
!AND NOT, !OR NOT
!OUT, !OUT NOT
Differentiated up / !@LD, !@AND, !@OR
immediate refresh
Differentiated down / !%LD, !%AND, !%OR
immediate refresh
158
Immediate refresh instructions cannot be used for Units on Slave Racks.
Mnemonic
The ON/OFF status of the specified bit
is taken by the CPU with cyclic refresh-
ing, and it is reflected in the next instruc-
tion execution.
After the instruction is executed, the ON/
OFF status of the specified bit is output
with the next cyclic refreshing.
The instruction is executed once when
the specified bit turns from OFF to ON
and the ON state is held for one cycle.
The instruction is executed once when
the specified bit turns from ON to OFF
and the ON state is held for one cycle.
The input data for the specified bit is
taken by the CPU and the instruction is
executed.
After the instruction is executed, the
data for the specified bit is output.
The input data for the specified bit is
refreshed by the CPU, and the instruc-
tion is executed once when the bit turns
from OFF to ON and the ON state is
held for one cycle.
The input data for the specified bit is
refreshed by the CPU, and the instruc-
tion is executed once when the bit turns
from ON to OFF and the ON state is
held for one cycle.
Function
Cyclic refreshing
Before instruction execu-
tion
After instruction execution
Before instruction execu-
tion
Section 3-3
I/O refresh