Omron CS1G/H-CPUxxH Instructions Manual page 195

Sequence Output Instructions
Description
Flags
Precautions
174
Area
Index Registers
Indirect addressing
using Index Registers
When the execution condition goes from OFF to ON, DIFU(013) turns B ON.
When DIFU(013) is reached in the next cycle, B is turned OFF.
Execution condition
Status of B
When the execution condition goes from ON to OFF, DIFD(014) turns B ON.
When DIFD(014) is reached in the next cycle, B is turned OFF.
Execution condition
Status of B
DIFU(013) and DIFD(014) have immediate refreshing variations (!DIFU(013)
and !DIFD(014)). When an external output bit has been specified for B in one
of these instructions, any changes to B will be refreshed when the instruction
is executed and reflected immediately in the output bit. (The changes will not
be reflected immediately if the bit is allocated to a Group-2 High-density I/O
Unit, High-density Special I/O Unit, or a Unit mounted in a SYSMAC BUS
Remote I/O Slave Rack.)
UP(521) and DOWN(522) can be used to execute an instruction for just one
cycle when the execution condition goes from OFF → ON or ON → OFF.
Refer to 3-3-13 CONDITION ON/OFF: UP(521) and DOWN(522) for details.
No flags are affected by DIFU(013) and DIFD(014).
The operation of DIFU(013) or DIFD(014) depends on the execution condition
for the instruction itself as well as the execution condition for the program sec-
tion when it is programmed in an interlocked program section, a jumped pro-
gram section, or a subroutine. Refer to 3-5-3 INTERLOCK and INTERLOCK
CLEAR: IL(002) and ILC(003), 3-5-4 JUMP and JUMP END: JMP(004) and
JME(005), and 3-20 Interrupt Control Instructions for details.
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,IR0 to ,IR15
–2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to ,15–(– –) IR
1 cycle
Section 3-4
B
1 cycle