Omron CS1G/H-CPUxxH Instructions Manual page 265

Sysmac cs series; sysmac cj series

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Timer and Counter Instructions

The timer or counter instruction won't be executed if the PLC memory address

in the specified Index Register is not the address of a timer or counter PV.

Using Index Registers to indirectly address timers and counters can reduce

the size of the program and increase flexibility. For example, common subrou-

tines can be created.

The following example shows a program section that uses indirect addressing

to define and start 100 timers with SVs contained in D00100 through D00199.

IR0 contains the PLC memory address of the timer PV and IR1 contains the

PLC memory address of the timer Completion Flag.

1. MOVRW(561) moves the PLC memory address of the PV for timer T0000

to IR0. Afterwards IR0 can be used in place of the timer number.

SV for T0000

SV for T0001

SV for T0002

SV for T0099

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