Omron CS1G/H-CPUxxH Instructions Manual page 248

Timer and Counter Instructions
Operand Specifications
S: First SV Word
S through S+7 contain the eight independent SVs.
Each SV must be as follows:
Data
BCD
Binary
Data
BCD
Binary
Note S through S+7 must be in the same data area.
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
EM Area without bank
EM Area with bank
Indirect DM/EM addresses in
binary
Indirect DM/EM addresses in
BCD
Constants
Data Registers
Range
#0000 to #9999
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Corresponding bit
(Completion Flag) in D1
Range
One word for each of 8 timer SV:
#0000 to #9999
One word for each of 8 timer SV:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
D1
CIO 0000 to CIO 6143
W000 to W511
H000 to H511
A448 to A959
T0000 to T4095
C0000 to C4095
D00000 to D32767
E00000 to E32767
En_00000 to En_32767
(n = 0 to C)
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
---
---
Section 3-6
D2 S
CIO 0000 to
CIO 6136
W000 to W504
H000 to H504
A000 to A952
T0000 to T4088
C0000 to C4088
D00000 to
D32760
E00000 to
E32760
En_00000 to
En_32760
(n = 0 to C)
DR0 to DR15 ---
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