Omron CS1G/H-CPUxxH Instructions Manual page 244

Timer and Counter Instructions
Variations
Applicable Program Areas
Operands
Operand Specifications
Binary
Variations Executed Each Cycle for ON Condition
Executed Once for Upward Differentiation
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification
Block program areas
Not allowed OK
D1: Completion Flag
Bit 0 of D1 acts as the Completion Flag for TIML(542)/TIMLX(553).
15
D1
D2: PV Word
D2+1 and D2 contain the 8-digit binary or BCD PV. (D2 and D2+1 must be in
the same data area.) The PV can range from #00000000 to #99999999 for
TIML(542) and &00000000 to &4294967294 (decimal) or #00000000 to
#FFFFFFFF (hexadecimal) for TIMLX(553).
D2
S: SV Word
S+1 and S contain the 8-digit binary or BCD SV. (S and S+1 must be in the
same data area.) The SV must be between #00000000 to #99999999 for
TIML(542) and &00000000 to &4294967294 (decimal) or #00000000 to
#FFFFFFFF (hexadecimal) for TIMLX(553).
S
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
EM Area without bank
TIMLX(543)
D1
D1: Completion Flag
D2 D2: PV word
S S: SV word
Step program areas Subroutines
OK
0
Do not use.
D2+1
S+1
D1
CIO 0000 to CIO 0000 to CIO 6142
CIO 6143
W000 to W511 W000 to W510
H000 to H511 H000 to H510
A448 to A959 A448 to A958
--- ---
--- ---
D00000 to D00000 to D32766
D32767
E00000 to E00000 to E32766
E32767
Section 3-6
TIML(542)/
TIMLX(553)
Not supported.
Not supported.
Interrupt tasks
Not allowed
Completion Flag
D2
S
D2 S
A000 to A958
T0000 to T4094
C0000 to C4094
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