Omron CS1G/H-CPUxxH Instructions Manual page 262

Sysmac cs series; sysmac cj series

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Timer and Counter Instructions

Two-stage Counter

Clock Pulse and CNT Instruction

In this example, a CNT instruction counts the pulses from the 1-s clock pulse

to make a 700-second timer.

If the First Cycle Flag (A20011) is ORed with the counter's reset input

(CIO 000001), the counter's PV will be reset to the SV (0700) when program

execution begins rather than resuming the count from the previous PV.

1 s (1-s clock)

When an SV higher than 9999 is required, two counters can be combined as

shown in the following example. In this case, two CNT instructions are com-

bined to make a BCD counter with an SV of 20,000.

Address Instruction Operands

Address Instruction Operands

Address Instruction

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