Omron CS1G/H-CPUxxH Instructions Manual page 243

Timer and Counter Instructions
Example
Timer input
CIO 000000
Timer PV
#
T0001
Timer Completion
Flag
T0001
Reset input
CIO 000001
3-6-5 LONG TIMER: TIML(542)/TIMLX(553)
Purpose
Ladder Symbol
222
The timer's Completion Flag is refreshed only when TTIM(087)/TTIMX(555) is
executed, so a delay of up to one cycle may be required for the Completion
Flag to be turned ON after the timer times out.
Typical timers such as TIM/TIMX(550) are decrementing counters and the PV
shows the time remaining until the timer times out. The PV of TTIM(087)/
TTIMX(555) shows how much time has elapsed, so the PV can be used
unchanged in many calculations and display outputs.
When timer input CIO 000000 is ON in the following example, the timer PV
will begin counting up from 0. Timer Completion Flag T0001 will be turned ON
when the PV reaches the SV.
If the reset input is turned ON, the timer PV will be reset to 0000 and the Com-
pletion Flag (T0001) will be turned OFF. (Usually the reset input is turned ON
to reset the timer and then the timer input is turned ON to start timing.)
If the timer input is turned OFF before the SV is reached, the timer will stop
timing but the PV will be maintained. The timer will resume from its previous
PV when the timer input is turned ON again.
#
TIML(542)/TIMLX(553) operates a decrementing timer with units of 1 s that
can time up to 115 days for TIML(542) and 49,710 days for TIMLX(543). The
timer accuracy is 0 to 0.01 s.
Note The timer accuracy for CS1D CPU Units is 10 ms + the cycle time
BCD
TIML(542)
D1: Completion Flag
D1
D2: PV word
D2
S: SV word
S
Section 3-6
Timing resumes.
PV maintained.