General Specifications; Table 4-8. Interface Specifications; Figure 4-3. Hssi Interface Block Diagram - Comtech EF Data CDM-Qx Installation And Operation Manual

CDM-Qx Satellite Modem
External Connections
J1
TT
SD
ST
TA
CA
RT
RD
Common
4.4.10.1
Item
Data Rate Range
Signals Supported
Connector
Electrical
Electrical Typical
Minimum Buffer Size
Impedance Tx
Rx
Signal Characteristics
Clock / Data Relationship The data transitions occur during the OFF to ON transition of the clock. Data is stable
Tx Clock Modes
Rx Clock Modes
Tx / Rx Clock
TA / CA Default
Selection
Tx Clock Input (External)
Tx Data
Output Clock (Rate Programmable)
(RTS)
(CTS)
Rx Clock
Rx Data

Figure 4-3. HSSI Interface Block Diagram

General Specifications

Table 4-8. Interface Specifications

Requirement
32 to 20 Mbps
ST, TT (or external) , SD, TA, CA, RT, RD, SG
DCE, 50-pin mini-D female per EIA-613 (HSSI)
Per EIA-612 (10KH ECL compatible).
Differential output voltage: > 590 mV pp into 110Ω load
Differential Input voltage: 150 to 1000 mV pp with 110Ω load
5.0 mS smallest buffer setting, 0.1 mS step size, 32 mS maximum size
110Ω for TT, SD, TA
ST, CA, RT, RD will drive 110Ω and meet HSSI voltage levels
The A terminal is negative with respect to the B terminal for a binary 0 (Space or OFF) state.
The A terminal is positive with respect to the B Terminal for a binary 1 (Mark or ON) state.
during the ON to Off transition of the clock.
TT (Input clock) continuous.
ST (output clock) is continuous output, programmable in 1 bps steps or phase locked to
satellite clock
RT (output clock) is continuous from satellite, ST (internal clock), continuous from TT
Asymmetrical clocking with Rx Doppler buffer disabled
CA looped to TA
CA is asserted when there is no modem fault
Processor
Processor
Mux /
Mux /
Demux
Demux
PLL
PLL
Rx
Rx
Buffer
Buffer
Interface
Interface
Loopback
Loopback
Control
Control
HSSI Interface
4–12
Revision 6
MN/CDMQx.IOM
Clk
&
Data
Modem
Interface
μC