Clock; Phase Lock Loop (Pll); Clock Signals; Phase Lock Loop Signals - Motorola DSP56303 User Manual

2.3

Clock

Signal
Type
Name
EXTAL Input Input
XTAL Output Chip-driven
2.4

Phase Lock Loop (PLL)

Signal Name Type
PCAP Input
CLKOUT Output
PINIT/NMI Input
Table 2-4. Clock Signals
State During
Reset
External Clock/Crystal Input—Interfaces the internal crystal oscillator
input to an external crystal or an external clock.
Crystal Output—Connects the internal crystal oscillator output to an
external crystal. If an external clock is used, leave XTAL unconnected.
Table 2-5. Phase Lock Loop Signals
State During
Reset
Input PLL Capacitor—Connects an off-chip capacitor to the PLL filter. See
the DSP56303 Technical Data sheet to determine the correct PLL
capacitor value. Connect one capacitor terminal to PCAP and the
other terminal to V
If the PLL is not used, PCAP can be tied to V
Chip-driven Clock Output—Provides an output clock synchronized to the internal
core clock phase.
If the PLL is enabled and both the multiplication and division factors
equal one, then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of
EXTAL.
Input PLL Initial/Non-Maskable Interrupt—During assertion of RESET,
the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the
PLL control register, determining whether the PLL is enabled or
disabled. After RESET deassertion and during normal instruction
processing, the PINIT/NMI Schmitt-trigger input is a
negative-edge-triggered Non-Maskable Interrupt (NMI) request
internally synchronized to CLKOUT.
PINIT/NMI can tolerate 5 V.
Signals/Connections
Signal Description
Signal Description
.
CCP
CC
Clock
, GND, or left floating.
2-5