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Exceptions
8.4.2
Bootstrap Loading Through the SCI (Boot Mode 2 or A)
When the DSP comes out of reset, it checks the MODD, MODC, MODB, and MODA pins
and sets the corresponding mode bits in the Operating Mode Register (OMR). If the mode bits
are write to 0010 or 1010, respectively, the DSP loads the program RAM from the SCI.
Appendix shows the complete bootstrap code. This program (1) configures the SCI, (2)
loads the program size, (3) loads the location where the program begins loading in program
memory, and (4) loads the program.
First, the SCI Control Register is set to $000302, which enables the transmitter and receiver
and configures the SCI for 10 bits asynchronous with one start bit, 8 data bits, one stop bit,
and no parity. Next, the SCI Clock Control Register is set to $00C000, which configures the
SCI to use external receive and transmit clocks from the
must be 16 times the desired serial data rate.
The next step is to receive the program size and then the starting address to load the program.
These two numbers are three bytes each loaded least significant byte first. Each byte is echoed
back as it is received. After both numbers are loaded, the program size is in A0 and the
starting address is in A1.
The program is then loaded one byte at a time, least significant byte first. After the program is
loaded, the operating mode is set to zero, the CCR is cleared, and the DSP begins execution
with the first instruction loaded
8.5
Exceptions
The SCI can cause five different exceptions in the DSP, discussed here from the highest to the
lowest priority:
1.
SCI receive data with exception status occurs when the receive data register is full with
a receiver error (parity, framing, or overrun error). To clear the pending interrupt, read
the SCI status register; then read SRX. Use a long interrupt service routine to handle
the error condition. This interrupt is enabled by SCR[16] (REIE).
2.
SCI receive data occurs when the receive data register is full. Read SRX to clear the pending
interrupt. This error-free interrupt can use a fast interrupt service routine for minimum over-
head. This interrupt is enabled by SCR[11] (RIE).
3.
SCI transmit data occurs when the transmit data register is empty. Write STX to clear the
pending interrupt. This error-free interrupt can use a fast interrupt service routine for mini-
mum overhead. This interrupt is enabled by SCR[12] (TIE).
4.
SCI idle line occurs when the receive line enters the idle state (10 or 11 bits of ones). This
interrupt is latched and then automatically reset when the interrupt is accepted. This interrupt
is enabled by SCR[10] (ILIE).
8-8
DSP56303 User's Manual
pin input. This external clock
SCLK
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