Motorola DSP56303 User Manual page 79

Table 4-2. Status Register Bit Definitions (Continued)
Bit Number Bit Name
11–10 S[1–0]
9–8 I[1–0]
7 S
Reset Value
0 Scaling Mode
Specify the scaling to be performed in the Data ALU shifter/limiter and the
rounding position in the Data ALU MAC unit. The Shifter/limiter Scaling
mode affects data read from the A or B accumulator registers out to the
X-data bus (XDB) and Y-data bus (YDB). Different scaling modes can be
used with the same program code to allow dynamic scaling. One
application of dynamic scaling is to facilitate block floating-point arithmetic.
The scaling mode also affects the MAC rounding position to maintain
proper rounding when different portions of the accumulator registers are
read out to the XDB and YDB. Scaling mode bits are cleared at the start of
a long Interrupt Service Routine and during a hardware reset.
S1
0
0
1
1
11 Interrupt Mask
Reflect the current Interrupt Priority Level (IPL) of the processor and
indicate the IPL needed for an interrupt source to interrupt the processor.
The current IPL of the processor can be changed under software control.
The interrupt mask bits are set during hardware reset, but not during
software reset.
Priority
Lowest
Highest
0 Scaling
Set when a result moves from accumulator A or B to the XDB or YDB buses
(during an accumulator to memory or accumulator to register move) and
remains set until explicitly cleared; that is, the S bit is a sticky bit . The
logical equations of this bit are dependent on the Scaling mode. The scaling
bit is set if the absolute value in the accumulator, before scaling, is > 0.25 or
< 0.75.
Core Configuration
Central Processor Unit (CPU) Registers
Description
Scaling
S0 Rounding Bit
Mode
0 No scaling
1 Scale down
0 Scale up
1 Reserved
Exceptions
I1 I0
Permitted
0 0
IPL 0, 1, 2, 3
0 1
IPL 1, 2, 3
1 0
IPL 2, 3
1 1
IPL 3
SEquation
23 S = (A46 XOR A45)
OR (B46 XOR B45)
OR S (previous)
24 S = (A47 XOR A46)
OR (B47 XOR B46)
OR S (previous)
22 S = (A45 XOR A44)
OR (B45 XOR B44)
OR S (previous)
— S undefined
Exceptions Masked
None
IPL 0
IPL 0, 1
IPL 0, 1, 2
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